Analog-Digital System Modeling for Electromagnetic Susceptibility Prediction

The thesis is focused on the noise susceptibility of communication networks. These analog-mixed signal systems operate in an electrically noisy environment, in presence of multiple equipments connected by means of long wiring. Every module communicates using a transceiver as an interface between the local digital signaling and the data transmission through the network. Hence, the performance of the IC transceiver when affected by disturbances is one of the main factors that guarantees the EM immunity of the whole equipment. The susceptibility to RF and transient disturbances is addressed at component level on a CAN transceiver as a test case, highlighting the IC features critical for noise immunity. A novel procedure is proposed for the IC modeling for mixed-signal immunity simulations of communication networks. The procedure is based on a gray-box approach, modeling IC ports with a physical circuit and the internal links with a behavioural block. The parameters are estimated from time and frequency domain measurements, allowing accurate and efficient reproduction of non-linear device switching behaviours. The effectiveness of the modeling process is verified by applying the proposed technique to a CAN transceiver, involved in a real immunity test on a data communication link. The obtained model is successfully implemented in a commercial solver to predict both the functional signals and the RF noise immunity at component level. The noise immunity at system level is then evaluated on a complete communication network, analyzing the results of several tests on a realistic CAN bus. After developing models for wires and injection probes, a noise immunity test in avionic environment is carried out in a simulation environment, observing good overall accuracy and efficiency

inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices

Transistor technology scaling has been the driving force in improving the size, speed, and power consumption of digital systems. As devices approach atomic size, however, their reliability and performance are increasingly compromised due to reduced noise margins, difficulties in fabrication, and emergent nano-scale phenomena. Scaled CMOS devices, in particular, suffer from process variations such as random dopant fluctuation (RDF) and line edge roughness (LER), transistor degradation mechanisms such as negative-bias temperature instability (NBTI) and hot-carrier injection (HCI), and increased sensitivity to single event upsets (SEUs). Consequently, future devices may exhibit reduced performance, diminished lifetimes, and poor reliability. This research proposes a variation and fault tolerant architecture, the inSense architecture, as a circuit-level solution to the problems induced by the aforementioned phenomena. The inSense architecture entails augmenting circuits with introspective and sensory capabilities which are able to dynamically detect and compensate for process variations, transistor degradation, and soft errors. This approach creates ``smart\u27\u27 circuits able to function despite the use of unreliable devices and is applicable to current CMOS technology as well as next-generation devices using new materials and structures. Furthermore, this work presents an automated prototype implementation of the inSense architecture targeted to CMOS devices and is evaluated via implementation in ISCAS \u2785 benchmark circuits. The automated prototype implementation is functionally verified and characterized: it is found that error detection capability (with error windows from $\approx$30-400ps) can be added for less than 2\% area overhead for circuits of non-trivial complexity. Single event transient (SET) detection capability (configurable with target set-points) is found to be functional, although it generally tracks the standard DMR implementation with respect to overheads

In situ diagnostics and prognostics of wire bonding faults in IGBT modules for electric vehicle drives

This paper presents a diagnostic and prognostic condition monitoring method for insulated-gate bipolar transistor (IGBT) power modules for use primarily in electric vehicle applications. The wire-bond-related failure, one of the most commonly observed packaging failures, is investigated by analytical and experimental methods using the on-state voltage drop as a failure indicator. A sophisticated test bench is developed to generate and apply the required current/power pulses to the device under test. The proposed method is capable of detecting small changes in the failure indicators of the IGBTs and freewheeling diodes and its effectiveness is validated experimentally. The novelty of the work lies in the accurate online testing capacity for diagnostics and prognostics of the power module with a focus on the wire bonding faults, by injecting external currents into the power unit during the idle time. Test results show that the IGBT may sustain a loss of half the bond wires before the impending fault becomes catastrophic. The measurement circuitry can be embedded in the IGBT drive circuits and the measurements can be performed in situ when the electric vehicle stops in stop-and-go, red light traffic conditions, or during routine servicing

Piezoelectric Transformer and Hall-Effect Based Sensing and Disturbance Monitoring Methodology for High-Voltage Power Supply Lines

Advancements in relaying algorithms have led to an accurate and robust protection system widely used in power distribution. However, in low power sections of relaying systems, standard voltage and current measurement techniques are still used. These techniques have disadvantages like higher cost, size, electromagnetic interference, resistive losses and measurement errors and hence provide a number of opportunities for improvement and integration. We present a novel microsystem methodology to sense low-power voltage and current signals and detect disturbances in high-voltage power distribution lines. The system employs dual sensor architecture that consists of a piezoelectric transformer in combination with Hall-effect sensor, used to detect the disturbances whose harmonics are in the kHz frequency range. Our numerical analysis is based on three-dimensional finite element models of the piezoelectric transformer (PT) and the principle of Hall-effect based “Integrated Magnetic Concentrator (IMC)” sensor. This model is verified by using experimental data recorded in the resonant frequency and low frequency regions of operation of PT for voltage sensing. Actual measurements with the commercial IMC sensor too validate the modelling results. These results describe a characteristic low frequency behaviour of rectangular piezoelectric transformer, which enables it to withstand voltages as high as 150V. In the frequency range of 10Hz to 250Hz, the PT steps down 10-150V input with a linearity of ±1%. The recorded group delay data shows that propagation delay through PT reduces to few microseconds above 1kHz input signal frequency. Similarly, the non-intrusive current sensor detects current with a response time of 8μs and converts the current into corresponding output voltage. These properties, in addition to frequency spectrum of voltage and current input signals, have been used to develop a signal processing and fault detection system for two real-time cases of faults to produce a 6-bit decision logic capable of detecting various types of line disturbances in less than 3ms of delay

Electrical Optimization of a Plug-In Hybrid Electric Vehicle

Hybrid electric vehicles electrification and optimization is a prominent part of today’s automotive industry. GM and the Department of Energy challenge 16 universities across North America to redesign a Chevrolet Camaro into a hybrid electric vehicle. This thesis will address how Embry Riddle Aeronautical University’s EcoCAR team electrified and optimized the vehicle. The objective of the thesis is to optimize the electric portion of the vehicle, particularly the low voltage circuitry. Prior work is discussed in detail on the vehicle communication bus, building the power distribution unit and the approach the electrical team took when building the electric portion of the vehicle. Simulations were done based on manufacturer data and bench tests to create an ideal model. Data was collected from the vehicle and compared to the ideal model to determine errors in the electrical system. An emphasis was placed on critical and high power components to simplify the simulation model. The issues found were alleviated by conducting research, using research analysis, physically changing the system or by implementing control strategies. Most of the issues came from the power distribution unit and implementation techniques such as grounding. The MOSFETs within the power distribution unit was not fully turning on and off, and which was due to a slow RC time constant occurring on the gate of the transistors. By replacing the resistors, this issue was mitigated. Every problem found was properly mitigated to an acceptable industry or research standard

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

Real Time Testing and Validation of a Novel Short Circuit Current (SCC) Controller for a Photovoltaic Inverter

About 45% applications from PV solar farm developers seeking connections to the distribution grids in Ontario were denied in 2011-13 as the short circuit current (SCC) capacity of several distribution substations had already been reached. PV solar system inverters typically contribute 1.2 p.u. to 1.8 p.u. fault current which was not considered acceptable by utility companies due to the need for very expensive protective breaker upgrades. Since then, this cause has become a major impediment in the growth of PV based renewable systems in Ontario. A novel predictive technique has been patented in our research group for management of short circuit current contribution from PV inverters to ensure effective deployment of solar farms. This thesis deals with the real time testing and validation of a short circuit current (SCC) controller based on the above technique. With this SCC controller, the PV inverter can be shut off within 1-2 milliseconds from the initiation of any fault in the grid that can cause the short circuit current to exceed the rated current of the inverter. Therefore, the power system does not see any short circuit current contribution from the PV inverter and no expensive upgrades in protective breakers are required in the system. The performance of the PV solar system with the short circuit current controller is simulated and tested using (i) industry grade electromagnetic transients software PSCAD/EMTDC (ii) real time simulation studies on the Real Time Digital Simulator (RTDS) (iii) physical implementation on dSPACE board to generate firing pulses for the inverter. The validation of controller is done on dSPACE board with actual PV inverter short circuit waveforms obtained from Southern California Edison Short Circuit Testing Lab. This novel technology is planned to be showcased on a physical 10 kW PV solar system in Bluewater Power Distribution Corporation, Sarnia, Ontario. This proposed technology is expected to remove the technical hurdles which caused the denials of connectivity to several PV solar farms, and effectively lead to greater connections of PV solar farms in Ontario and in similar jurisdictions, worldwide

An Integrated IGBT Active Gate Driver with Fast Feed-Forward Variable Current

The Insulated-Gate Bipolar Transistor (IGBT) is a hybrid of bipolar and MOSFET transistors. As a consequence, IGBTs can handle higher current typical of bipolar transistors with the ease of control typical of MOSFETs. These characteristics make IGBTs desirable for high power Switch Mode Power Supplies (SMPS). In high power systems such as these, devices must be very reliable, as device failures may result in safety hazards such as fires in addition to the failure of the system. Conventional Gate Driver (CGD) circuits typically design for reliability in these systems by including a resistor between the gate driver and gate of the IGBT. This slows the switching waveforms, reducing stress on the IGBT while sacrificing efficiency. This solution is suboptimal, however, and as such Active Gate Drivers (AGD) have been designed to control voltage and current slopes through the IGBT by modulating the gate signal. AGD circuits found on the market today consist of a combination of an CGD with external components to implement the variable current necessary for protection. This requires a large amount of area on a Printed Circuit Board (PCB), and thus can be costly. Therefore, it can be desirable to integrate the AGD functionality into an on-chip system. In this thesis, an AGD is designed, fabricated and analyzed to show that IGBT gate voltage can be controlled in a manner capable of reducing overvoltage, as well as slowed when desired using an on-chip system. The current provided by this gate driver is controlled by feedback signals indicating the switching state of the device, as well as input bits that determine total output current

Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault-Injection

International audienceLaser fault injections induce transient faults into ICs by locally generating transient currents that temporarily flip the outputs of the illuminated gates. Laser fault injection can be anticipated or studied by using simulation tools at different abstraction levels: physical, electrical or logical. At the electrical level, the classical laser-fault injection model is based on the addition of current sources to the various sensitive nodes of CMOS transistors. However, this model does not take into account the large transient current components also induced between the VDD and GND of ICs designed with advanced CMOS technologies. These short-circuit currents provoke a significant IR-drop that contribute to the fault injection process. This paper describes our research on the assessment of this contribution. It shows through simulation and experiments that during laser fault injection campaigns, laser-induced IR-drop is always present when considering circuits designed with deep submicron technologies. It introduces an enhanced electrical fault model taking the laser-induced IR-drop into account. It also proposes a methodology that allows the use of the model to simulate laser-induced faults at the electrical level in large-scale circuits. On the basis of further simulations and experimental results, we found that, depending on the laser pulse characteristics, the number of injected faults may be underestimated by a factor of up to 2.4 if the laser-induced IR-drop is ignored. This could lead to incorrect estimations of the fault injection threshold, which is especially relevant to the design of countermeasure techniques for secure integrated systems