Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

Statistical modelling of nano CMOS transistors with surface potential compact model PSP

The development of a statistical compact model strategy for nano-scale CMOS transistors is presented in this thesis. Statistical variability which arises from the discreteness of charge and granularity of matter plays an important role in scaling of nano CMOS transistors especially in sub 50nm technology nodes. In order to achieve reasonable performance and yield in contemporary CMOS designs, the statistical variability that affects the circuit/system performance and yield must be accurately represented by the industry standard compact models. As a starting point, predictive 3D simulation of an ensemble of 1000 microscopically different 35nm gate length transistors is carried out to characterize the impact of statistical variability on the device characteristics. PSP, an advanced surface potential compact model that is selected as the next generation industry standard compact model, is targeted in this study. There are two challenges in development of a statistical compact model strategy. The first challenge is related to the selection of a small subset of statistical compact model parameters from the large number of compact model parameters. We propose a strategy to select 7 parameters from PSP to capture the impact of statistical variability on current-voltage characteristics. These 7 parameters are used in statistical parameter extraction with an average RMS error of less than 2.5% crossing the whole operation region of the simulated transistors. Moreover, the accuracy of statistical compact model extraction strategy in reproducing the MOSFET electrical figures of merit is studied in detail. The results of the statistical compact model extraction are used for statistical circuit simulation of a CMOS inverter under different input-output conditions and different number of statistical parameters. The second challenge in the development of statistical compact model strategy is associated with statistical generation of parameters preserving the distribution and correlation of the directly extracted parameters. By using advanced statistical methods such as principal component analysis and nonlinear power method, the accuracy of parameter generation is evaluated and compared to directly extracted parameter sets. Finally, an extension of the PSP statistical compact model strategy to different channel width/length devices is presented. The statistical trends of parameters and figures of merit versus channel width/length are characterized

Multilevel Modeling and Architectural Solutions for Emerging Technology Circuits

In the last decades, the main driving force behind the astonishing development of CMOS technology, was the transistor scaling process. The reduction of transistor sizes has granted a continuous boost in circuits performance. But now that the scaling process is reaching its physical limits, researchers are forcusing on new emerging technologies. Research on these new technologies is usually carried on using a traditional approach. Some studies concentrate on new devices without analyzing circuits based on them. Other studies analyze circuit architectures without considering devices characteristics and limitations. However, given that the nature of emerging technologies can be very different from CMOS, new research methodologies should be adopted. A clear link between device and architectural analysis is necessary to understand the true potential of the technology under study. The objective of this PhD thesis is the analysis of emerging technologies using an innovative methodology. Using complex and realistic circuits as benchmark, high level models are built incorporating low level device characteristics. This methodology strongly links device and architectural levels. The methodology was applied to two emerging technologies: NanoMagnet Logic (NML) and Nanoscale Application Specific Integrated Circuits (NASIC). A brief introduction of fundamental information on the two technologies is given in Chapter 1. The application of the methodology on NML technology is divided in two parts (Chapter 2): i) architecture-level timing and performance analysis and circuits optimization; (ii) area and power estimations using VHDL modeling. Starting from an exhaustive analysis of the effects and the consequences derived by the presence of loops in a complex NML sequential architecture, solutions have been proposed to address the problem of signal synchronization, and optimization techniques have been explored for performance maximization. Area and power estimations have been performed on multiple NML architectures in order to obtain a complete evaluation on the implementation of NanoMagnet Logic in comparison with the CMOS technology. Chapter 4 is dedicated to NASIC technology with basic principles described in Chapter 3. Basic computational blocks are implemented using a multilevel modeling approach. A detailed analysis of circuits' area and power estimations is obtained. Techniques to optimize the area of circuits at the cost of reduced throughput were also investigated. The research activity presented in this thesis highlights the development of an innovative methodology based on high-level models that embed information obtained from physical level simulations. By exploiting this methodology to different emerging technologies, such as NML and NASIC, it allows to eciently analyze circuits and therefore to bring architectural improvements

Statistical compact model strategies for nano CMOS transistors subject of atomic scale variability

One of the major limiting factors of the CMOS device, circuit and system simulation in sub 100nm regimes is the statistical variability introduced by the discreteness of charge and granularity of matter. The statistical variability cannot be eliminated by tuning the layout or by tightening fabrication process control. Since the compact models are the key bridge between technology and design, it is necessary to transfer reliably the MOSFET statistical variability information into compact models to facilitate variability aware design practice. The aim of this project is the development of a statistical extraction methodology essential to capture statistical variability with optimum set of parameters particularly in industry standard compact model BSIM. This task is accomplished by using a detailed study on the sensitivity analysis of the transistor current in respect to key parameters in compact model in combination with error analysis of the fitted Id-Vg characteristics. The key point in the developed direct statistical compact model strategy is that the impacts of statistical variability can be captured in device characteristics by tuning a limited number of parameters and keeping the values for remaining major set equal to their default values obtained from the “uniform” MOSFET compact model extraction. However, the statistical compact model extraction strategies will accurately represent the distribution and correlation of the electrical MOSFET figures of merit. Statistical compact model parameters are generated using statistical parameter generation techniques such as uncorrelated parameter distributions, principal component analysis and nonlinear power method. The accuracy of these methods is evaluated in comparison with the results obtained from ‘atomistic’ simulations. The impact of the correlations in the compact model parameters has been analyzed along with the corresponding transistor figures of merit. The accuracy of the circuit simulations with different statistical compact model libraries has been studied. Moreover, the impact of the MOSFET width/length on the statistical trend of the optimum set of statistical compact model parameters and electrical figures of merit has been analyzed with two methods to capture geometry dependencies in proposed statistical models

Single Electron Devices and Circuit Architectures: Modeling Techniques, Dynamic Characteristics, and Reliability Analysis

The Single Electron (SE) technology is an important approach to enabling further feature size reduction and circuit performance improvement. However, new methods are required for device modeling, circuit behavior description, and reliability analysis with this technology due to its unique operation mechanism. In this thesis, a new macro-model of SE turnstile is developed to describe its physical characteristics for large-scale circuit simulation and design. Based on this model, several novel circuit architectures are proposed and implemented to further demonstrate the advantages of SE technique. The dynamic behavior of SE circuits, which is different from their CMOS counterpart, is also investigated using a statistical method. With the unreliable feature of SE devices in mind, a fast and recursive algorithm is developed to evaluate the reliability of SE logic circuits in a more efficient and effective manner

Imperfection-Aware Design of CNFET Digital VLSI Circuits

Carbon nanotube field-effect transistor (CNFET) is one of the promising candidates as extensions to silicon CMOS devices. The CNFET, which is a 1-D structure with a near-ballistic transport capability, can potentially offer excellent device characteristics and order-of-magnitude better energy-delay product over standard CMOS devices. Significant challenges in CNT synthesis prevent CNFETs today from achieving such ideal benefits. CNT density variation and metallic CNTs are the dominant type of CNT variations/imperfections that cause performance variation, large static power consumption, and yield degradation. We present an imperfection-aware design technique for CNFET digital VLSI circuits by: 1) Analytical models that are developed to analyze and quantify the effects of CNT density variation on device characteristics, gate and system levels delays. The analytical models, which were validated by comparison to real experimental/simulation data, enables us to examine the space of CNFET combinational, sequential and memory cells circuits to minimize delay variations. Using these model, we drive CNFET processing and circuit design guidelines to manage/overcome CNT density variation. 2) Analytical models that are developed to analyze the effects of metallic CNTs on device characteristics, gate and system levels delay and power consumption. Using our presented analytical models, which are again validated by comparison with simulation data, it is shown that the static power dissipation is a more critical issue than the delay and the dynamic power of CNFET circuits in the presence of m-CNTs. 3) CNT density variation and metallic CNTs can result in functional failure of CNFET circuits. The complete and compact model for CNFET probability of failure that consider CNT density variation and m-CNTs is presented. This analytical model is applied to analyze the logical functional failures. The presented model is extended to predict opportunities and limitations of CNFET technology at todays Gigascale integration and beyond.\u2