Fast detection of instability in sigma-delta modulators based on unstable embedded limit cycles

As a sequel to a previous study (Wong and Ng) on the nonlinear dynamical behavior of low-pass, high-order (order > 2), single-bit ΣΔ modulators with distinct unit-circle noise transfer function zeros, this paper proposes a novel scheme for the fast detection of unstable operation in these modulators under general time-varying input. The scheme is based on the variation of unstable embedded limit-cycle fixed points (which form the bounds beyond which the modulator becomes unstable) versus modulator input amplitude. Deployment of the detection scheme requires simple analog components with possible simplification. The effectiveness of the scheme is demonstrated with numerical examples. © 2004 IEEE.published_or_final_versio

Signal processing using short word-length

Recently short word-length (normally 1 bit or bits) processing has become a promising technique. However, there are unresolved issues in sigma-delta modulation, which is the basis for 1b/2b systems. These issues hindered the full adoption of single-bit techniues in industry. Among these problems is the stability of high-order modulators and the limit cycle behaviour. More importantly, there is no adaptive LMS structure of any kind in 1b/2b domain. The challenge in this problem is the harsh quantization that prevents straightforward LMS application. In this thesis, the focus has been made on three axes: designing new single-bit DSP applications, proposing novel approaches for stability analysis, and tacking the unresolved problems of 1b/2b adaptive filtering. Two structures for 1b digital comb filtering are proposed. A ternary DC blocker structure is also presented and performanc e is tested. We also proposed a single-bit multiplierless DC-blocking structure. The stability of a single-bit high-order signma-delta modulator is studied under dc inputs. A new approach for stability analysis is proposed based on analogy with PLL analysis. Finally we succeeded in designing 1b/2b Wiener-like filtering and introduced (for the first time) three 1b/2b adaptive schemes

Sigma delta modulation of a chaotic signal

Sigma delta modulation SDM has become a widespread method of analogue to digital conversion, however its operation has not been completely defined. The majority of the analysis carried out on the circuit has been from a linear standpoint, with non-linear analysis hinting at hidden complexities in the modulator's operation. The sigma delta modulator itself is a non-linear system consisting, as it does, of a number of integrators and a one bit quantiser in a feedback loop. This configuration can be generalised as a non-linearity within a feedback path, which is a classic route to chaotic behaviour. This initially raises the prospect that a sigma delta modulator may be capable of chaotic modes of operation with a non-chaotic input. In fact, the problem does not arise and we show why not. To facilitate this investigation, a set of differential equations is formulated to represent SDM; these equations are subsequently utilised in a stability study of the sigma delta modulator. Of more interest, and more uncertainty, is the effect sigma delta modulation may have on a chaotic signal. If SDM makes a chaotic signal more chaotic then this will have serious repercussions on the predictability of that signal. In the past, analysis of the circuit has tended to be based around a steady state input or a slowly moving non-chaotic input such as a low frequency sine wave. This has greatly eased the complexity of such analyses, but it does not address the problem at hand. In this thesis we present the results of comparing the sigma delta modulation of a chaotic signal to a direct quantisation of the same signal. The tool we use to investigate this is the Lyapunov spectrum of the time series, measured using an algorithm developed at Edinburgh University. The Lyapunov exponents of a chaotic signal are presented before and after both SDM and direct quantisation, and it is shown that SDM does not increase the chaos of the signal. Indeed, it is shown that SDM has no more effect on the predictability of the signal, as measured by the Lyapunov spectrum, than direct quantisation. As such, we conclude that sigma delta modulation provides a reliable method for analogue to digital conversion of chaotic signals. It should be pointed out that, due to the incompleteness of rigorous analysis of SDM and the complex processes involved in applying such analysis to a chaotic signal, the results of this thesis are largely based upon experimentation and observation from a simulation of a sigma delta modulator

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

Design, analysis and evaluation of sigma-delta based beamformers for medical ultrasound imaging applications

The inherent analogue nature of medical ultrasound signals in conjunction with the abundant merits provided by digital image acquisition, together with the increasing use of relatively simple front-end circuitries, have created considerable demand for single-bit beamformers in digital ultrasound imaging systems. Furthermore, the increasing need to design lightweight ultrasound systems with low power consumption and low noise, provide ample justification for development and innovation in the use of single-bit beamformers in ultrasound imaging systems. The overall aim of this research program is to investigate, establish, develop and confirm through a combination of theoretical analysis and detailed simulations, that utilize raw phantom data sets, suitable techniques for the design of simple-to-implement hardware efficient digital ultrasound beamformers to address the requirements for 3D scanners with large channel counts, as well as portable and lightweight ultrasound scanners for point-of-care applications and intravascular imaging systems. In addition, the stability boundaries of higher-order High-Pass (HP) and Band-Pass (BP) Σ−Δ modulators for single- and dual- sinusoidal inputs are determined using quasi-linear modeling together with the describing-function method, to more accurately model the modulator quantizer. The theoretical results are shown to be in good agreement with the simulation results for a variety of input amplitudes, bandwidths, and modulator orders. The proposed mathematical models of the quantizer will immensely help speed up the design of higher order HP and BP Σ−Δ modulators to be applicable for digital ultrasound beamformers. Finally, a user friendly design and performance evaluation tool for LP, BP and HP modulators is developed. This toolbox, which uses various design methodologies and covers an assortment of modulators topologies, is intended to accelerate the design process and evaluation of modulators. This design tool is further developed to enable the design, analysis and evaluation of beamformer structures including the noise analyses of the final B-scan images. Thus, this tool will allow researchers and practitioners to design and verify different reconstruction filters and analyze the results directly on the B-scan ultrasound images thereby saving considerable time and effort

Control of chaos in nonlinear circuits and systems

Nonlinear circuits and systems, such as electronic circuits (Chapter 5), power converters (Chapter 6), human brains (Chapter 7), phase lock loops (Chapter 8), sigma delta modulators (Chapter 9), etc, are found almost everywhere. Understanding nonlinear behaviours as well as control of these circuits and systems are important for real practical engineering applications. Control theories for linear circuits and systems are well developed and almost complete. However, different nonlinear circuits and systems could exhibit very different behaviours. Hence, it is difficult to unify a general control theory for general nonlinear circuits and systems. Up to now, control theories for nonlinear circuits and systems are still very limited. The objective of this book is to review the state of the art chaos control methods for some common nonlinear circuits and systems, such as those listed in the above, and stimulate further research and development in chaos control for nonlinear circuits and systems. This book consists of three parts. The first part of the book consists of reviews on general chaos control methods. In particular, a time-delayed approach written by H. Huang and G. Feng is reviewed in Chapter 1. A master slave synchronization problem for chaotic Lur’e systems is considered. A delay independent and delay dependent synchronization criteria are derived based on the H performance. The design of the time delayed feedback controller can be accomplished by means of the feasibility of linear matrix inequalities. In Chapter 2, a fuzzy model based approach written by H.K. Lam and F.H.F. Leung is reviewed. The synchronization of chaotic systems subject to parameter uncertainties is considered. A chaotic system is first represented by the fuzzy model. A switching controller is then employed to synchronize the systems. The stability conditions in terms of linear matrix inequalities are derived based on the Lyapunov stability theory. The tracking performance and parameter design of the controller are formulated as a generalized eigenvalue minimization problem which is solved numerically via some convex programming techniques. In Chapter 3, a sliding mode control approach written by Y. Feng and X. Yu is reviewed. Three kinds of sliding mode control methods, traditional sliding mode control, terminal sliding mode control and non-singular terminal sliding mode control, are employed for the control of a chaotic system to realize two different control objectives, namely to force the system states to converge to zero or to track desired trajectories. Observer based chaos synchronizations for chaotic systems with single nonlinearity and multi-nonlinearities are also presented. In Chapter 4, an optimal control approach written by C.Z. Wu, C.M. Liu, K.L. Teo and Q.X. Shao is reviewed. Systems with nonparametric regression with jump points are considered. The rough locations of all the possible jump points are identified using existing kernel methods. A smooth spline function is used to approximate each segment of the regression function. A time scaling transformation is derived so as to map the undecided jump points to fixed points. The approximation problem is formulated as an optimization problem and solved via existing optimization tools. The second part of the book consists of reviews on general chaos controls for continuous-time systems. In particular, chaos controls for Chua’s circuits written by L.A.B. Tôrres, L.A. Aguirre, R.M. Palhares and E.M.A.M. Mendes are discussed in Chapter 5. An inductorless Chua’s circuit realization is presented, as well as some practical issues, such as data analysis, mathematical modelling and dynamical characterization, are discussed. The tradeoff among the control objective, the control energy and the model complexity is derived. In Chapter 6, chaos controls for pulse width modulation current mode single phase H-bridge inverters written by B. Robert, M. Feki and H.H.C. Iu are discussed. A time delayed feedback controller is used in conjunction with the proportional controller in its simple form as well as in its extended form to stabilize the desired periodic orbit for larger values of the proportional controller gain. This method is very robust and easy to implement. In Chapter 7, chaos controls for epileptiform bursting in the brain written by M.W. Slutzky, P. Cvitanovic and D.J. Mogul are discussed. Chaos analysis and chaos control algorithms for manipulating the seizure like behaviour in a brain slice model are discussed. The techniques provide a nonlinear control pathway for terminating or potentially preventing epileptic seizures in the whole brain. The third part of the book consists of reviews on general chaos controls for discrete-time systems. In particular, chaos controls for phase lock loops written by A.M. Harb and B.A. Harb are discussed in Chapter 8. A nonlinear controller based on the theory of backstepping is designed so that the phase lock loops will not be out of lock. Also, the phase lock loops will not exhibit Hopf bifurcation and chaotic behaviours. In Chapter 9, chaos controls for sigma delta modulators written by B.W.K. Ling, C.Y.F. Ho and J.D. Reiss are discussed. A fuzzy impulsive control approach is employed for the control of the sigma delta modulators. The local stability criterion and the condition for the occurrence of limit cycle behaviours are derived. Based on the derived conditions, a fuzzy impulsive control law is formulated so that the occurrence of the limit cycle behaviours, the effect of the audio clicks and the distance between the state vectors and an invariant set are minimized supposing that the invariant set is nonempty. The state vectors can be bounded within any arbitrary nonempty region no matter what the input step size, the initial condition and the filter parameters are. The editors are much indebted to the editor of the World Scientific Series on Nonlinear Science, Prof. Leon Chua, and to Senior Editor Miss Lakshmi Narayan for their help and congenial processing of the edition

Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters

There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages of the delta-sigma ADC including relaxed anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and most importantly, reduced sensitivity to analog imperfections. In this thesis, several structures and design techniques are developed for the implementation of continuoustime (CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total power consumption, reduce the design complexity, and decrease the chip die area of delta-sigma modulators. First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad (SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of an Nth-order CT delta-sigma modulator, it requires only half the number of active amplifiers and feed-forward branches used in the conventional modulator architecture, thus decreasing the power consumption and area by reducing the number of amplifiers. The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder due to the reduced number of feedforward branches to its summing block. As a sequence, it consumes less power compared to a conventional CT adder. With a 130-nm CMOS technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz signal bandwidth and analog power dissipation lower than 12 mW. Presented as the second scheme to save power consumption and chip die area in ΔΣ modulators is a new stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique shares all the active blocks of the modulator second stage with its first stage during the two non-overlapping clock phases. Measurement results show that the modulator designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz conversion bandwidth dissipating less than 9 mW analog power

Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected

Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators

In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators. A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer coefficients but also exhibited greater robustness to non-idealties. Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work. In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator. This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio