Predictive control using an FPGA with application to aircraft control

Alternative and more efficient computational methods can extend the applicability of MPC to systems with tight real-time requirements. This paper presents a “system-on-a-chip” MPC system, implemented on a field programmable gate array (FPGA), consisting of a sparse structure-exploiting primal dual interior point (PDIP) QP solver for MPC reference tracking and a fast gradient QP solver for steady-state target calculation. A parallel reduced precision iterative solver is used to accelerate the solution of the set of linear equations forming the computational bottleneck of the PDIP algorithm. A numerical study of the effect of reducing the number of iterations highlights the effectiveness of the approach. The system is demonstrated with an FPGA-inthe-loop testbench controlling a nonlinear simulation of a large airliner. This study considers many more manipulated inputs than any previous FPGA-based MPC implementation to date, yet the implementation comfortably fits into a mid-range FPGA, and the controller compares well in terms of solution quality and latency to state-of-the-art QP solvers running on a standard PC

PI-BA Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization

Bundle adjustment (BA) is a fundamental optimization technique used in many crucial applications, including 3D scene reconstruction, robotic localization, camera calibration, autonomous driving, space exploration, street view map generation etc. Essentially, BA is a joint non-linear optimization problem, and one which can consume a significant amount of time and power, especially for large optimization problems. Previous approaches of optimizing BA performance heavily rely on parallel processing or distributed computing, which trade higher power consumption for higher performance. In this paper we propose {\pi}-BA, the first hardware-software co-designed BA engine on an embedded FPGA-SoC that exploits custom hardware for higher performance and power efficiency. Specifically, based on our key observation that not all points appear on all images in a BA problem, we designed and implemented a Co-Observation Optimization technique to accelerate BA operations with optimized usage of memory and computation resources. Experimental results confirm that {\pi}-BA outperforms the existing software implementations in terms of performance and power consumption.Comment: in Proceedings of IEEE FCCM 201

Computer Architectures to Close the Loop in Real-time Optimization

© 2015 IEEE.Many modern control, automation, signal processing and machine learning applications rely on solving a sequence of optimization problems, which are updated with measurements of a real system that evolves in time. The solutions of each of these optimization problems are then used to make decisions, which may be followed by changing some parameters of the physical system, thereby resulting in a feedback loop between the computing and the physical system. Real-time optimization is not the same as fast optimization, due to the fact that the computation is affected by an uncertain system that evolves in time. The suitability of a design should therefore not be judged from the optimality of a single optimization problem, but based on the evolution of the entire cyber-physical system. The algorithms and hardware used for solving a single optimization problem in the office might therefore be far from ideal when solving a sequence of real-time optimization problems. Instead of there being a single, optimal design, one has to trade-off a number of objectives, including performance, robustness, energy usage, size and cost. We therefore provide here a tutorial introduction to some of the questions and implementation issues that arise in real-time optimization applications. We will concentrate on some of the decisions that have to be made when designing the computing architecture and algorithm and argue that the choice of one informs the other

AN OPTIMIZED SQUARE ROOT ALGORITHM FOR IMPLEMENTATION IN FPGA HARDWARE

This paper presents an optimized digit-by-digit calculation method to solve complicated square root calculation in hardware, as a proposed simple algorithm for implementation in field programmable gate array (FPGA). The main principle of proposed method is two-bit shifting and subtracting-multiplexing operations, in order to achieve a simpler implementation and faster calculation. The proposed algorithm has conducted to implement FPGA based unsigned 32-bit and 64-bit binary square root successfully. The results have shown that proposed method is most efficient of hardware resource compare to other methods. In addition, the strategy can be expanded to larger number easily

Contribution to Efficient Use of Narrowband Radio Channel

Předkládaná práce se soustředí na problematiku využívání úzkopásmového rádiového kanálu rádiovými modemy, které jsou určené pro průmyslové aplikace pozemní pohyblivé rádiové služby, specifikované v dominantní míře Evropským standardem ETSI EN 300 113. Tato rádiová zařízení se používají v kmitočtových pásmech od 30 MHz do 1 GHz s nejčastěji přidělovanou šířkou pásma 25 kHz a ve většině svých instalací jsou využívána ve fixních nebo mobilních bezdrátových sítích. Mezi typické oblasti použití patří zejména datová telemetrie, aplikace typu SCADA, nebo monitorování transportu strategických surovin. Za hlavní znaky popisovaného systému lze označit komunikační pokrytí značných vzdáleností, dané především vysokou výkonovou účinnosti datového přenosu a využívaní efektivních přístupových technik na rádiový kanál se semiduplexním komunikačním režimem. Striktní požadavky na elektromagnetickou kompatibilitu umožňují těmto zařízením využívat spektrum i v oblastech kmitočtově blízkým jiným komunikačním systémům bez nutnosti vkládání dodatečných ochranných frekvenčních pásem. Úzkopásmové rádiové komunikační systémy, v současnosti používají převážně exponenciální digitální modulace s konstantní modulační obálkou zejména z důvodů velice striktních omezení pro velikost výkonu vyzářeného do sousedního kanálu. Dosahují tak pouze kompromisních hodnot komunikační účinnosti. Úpravy limitů příslušných rádiových parametrů a rychlý rozvoj prostředků číslicového zpracování signálu v nedávné době, dnes umožňují ekonomicky přijatelné využití spektrálně efektivnějších modulačních technik i v těch oblastech, kde je prioritní využívání úzkých rádiových kanálů. Cílem předkládané disertační práce je proto výzkum postupů směřující ke sjednocení výhodných vlastností lineárních a nelineárních modulací v moderní konstrukci úzkopásmového rádiového modemu. Účelem tohoto výzkumu je efektivní a „ekologické“ využívání přidělené části frekvenčního spektra. Mezi hlavní dílčí problémy, jimiž se předkládaná práce zabývá, lze zařadit zejména tyto: Nyquistova modulační filtrace, navrhovaná s ohledem na minimalizaci nežádoucích elektromagnetických interferencí, efektivní číslicové algoritmy frekvenční demodulace a rychlé rámcové a symbolové synchronizace. Součástí práce je dále analýza navrhovaného řešení z pohledu celkové konstrukce programově definovaného rádiového modemu v rovině simulací při vyšetřování robustnosti datového přenosu rádiovým kanálem s bílým Gaussovským šumem nebo kanálem s únikem v důsledku mnohacestného šíření signálu. Závěr práce je pak zaměřen na prezentování výsledků praktické části projektu, v níž byly testovány, měřeny a analyzovány dvě prototypové konstrukce rádiového zařízení. Tato finální část práce obsahuje i praktická doporučení, vedoucí k vyššímu stupni využitelnosti spektrálně efektivnějších komunikačních režimů v oblasti budoucí generace úzkopásmových zařízení pozemní pohyblivé rádiové služby.he industrial narrowband land mobile radio (LMR) devices, as considered in this dissertation project, has been subject to European standard ETSI EN 300 113. The system operates on frequencies between 30 MHz and 1 GHz, with channel separations of up to 25 kHz, and is intended for private, fixed, or mobile, radio packet switching networks. Data telemetry, SCADA, maritime and police radio services; traffic monitoring; gas, water, and electricity producing factories are the typical system applications. Long distance coverage, high power efficiency, and efficient channel access techniques in half duplex operation are the primary advantages the system relays on. Very low level of adjacent channel power emissions and robust radio receiver architectures, with high dynamic range, enable for a system’s coexistence with various communication standards, without the additional guard band frequency intervals. On the other hand, the strict limitations of the referenced standard as well as the state of the technology, has hindered the increase in communication efficiency, with which the system has used its occupied bandwidth. New modifications and improvements are needed to the standard itself and to the up-to-date architectures of narrowband LMR devices, to make the utilization of more efficient modes of system operation practically realizable. The main objective of this dissertation thesis is therefore to find a practical way how to combine the favorable properties of the advanced nonlinear and linear digital modulation techniques in a single digital modem solution, in order to increase the efficiency of the narrowband radio channel usage allocated to the new generation of the industrial LMR devices. The main attention is given to the particular areas of digital modem design such as proposal of the new family of the Nyquist filters minimizing the adjacent channel interference, design and analysis of the efficient algorithms for frequency discrimination, fast frame and symbol

Dadu-RBD: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines

Rigid body dynamics is a key technology in the robotics field. In trajectory optimization and model predictive control algorithms, there are usually a large number of rigid body dynamics computing tasks. Using CPUs to process these tasks consumes a lot of time, which will affect the real-time performance of robots. To this end, we propose a multifunctional robot rigid body dynamics accelerator, named RBDCore, to address the performance bottleneck. By analyzing different functions commonly used in robot dynamics calculations, we summarize their reuse relationship and optimize them according to the hardware. Based on this, RBDCore can fully reuse common hardware modules when processing different computing tasks. By dynamically switching the dataflow path, RBDCore can accelerate various dynamics functions without reconfiguring the hardware. We design Structure-Adaptive Pipelines for RBDCore, which can greatly improve the throughput of the accelerator. Robots with different structures and parameters can be optimized specifically. Compared with the state-of-the-art CPU, GPU dynamics libraries and FPGA accelerator, RBDCore can significantly improve the performance

Open-ended evolution to discover analogue circuits for beyond conventional applications

This is the author's accepted manuscript. The final publication is available at Springer via http://dx.doi.org/10.1007/s10710-012-9163-8. Copyright @ Springer 2012.Analogue circuits synthesised by means of open-ended evolutionary algorithms often have unconventional designs. However, these circuits are typically highly compact, and the general nature of the evolutionary search methodology allows such designs to be used in many applications. Previous work on the evolutionary design of analogue circuits has focused on circuits that lie well within analogue application domain. In contrast, our paper considers the evolution of analogue circuits that are usually synthesised in digital logic. We have developed four computational circuits, two voltage distributor circuits and a time interval metre circuit. The approach, despite its simplicity, succeeds over the design tasks owing to the employment of substructure reuse and incremental evolution. Our findings expand the range of applications that are considered suitable for evolutionary electronics