Implementation of a software defined radio on FPGAs using system generator

The aim of this thesis is to implement a Software Defined Radio based wireless communication system using a Xilinx Spartan 3E Field Programmable Gate Array. Software Defined Radio refers to the class of reprogrammable radios in which the same piece of hardware can perform different functions at different times. Xilinx’s System Generator for Digital Signal Processor tool is used to simulate and implement AM modulation on the Spartan 3E Starter Board. The aim of this thesis is to implement a Software Defined Radio based wireless communication system using a Xilinx Spartan 3E Field Programmable Gate Array. Software Defined Radio refers to the class of reprogrammable radios in which the same piece of hardware can perform different functions at different times. Xilinx’s System Generator for Digital Signal Processor tool is used to simulate and implement AM modulation on the Spartan 3E Starter Board

A CASE STUDY OF VARIOUS WIRELESS NETWORK SIMULATION TOOLS

4G is the fastest developing system in the history of mobile communication networks. Network connectivity is paramount for all kinds of big enterprises.  4G not only provides super-fast connectivity to millions of users, but can also act as an enterprise network connectivity enabler and it has inherent advantages such as higher bandwidth, low latency, higher spectrum efficiency along with backward compatibility and future proofing. The design of the 4G based Long Term Evolution physical network provides the required flexibility for optimization during the development phase. In this paper LTE Network related supporting simulation tools is presented to demonstrate the need of Hardware co-simulation of the LTE system. After the feasibility analysis, the importance of the model is to be ported Field Programmable Gate Array platform is examined in survey in detail with the supporting inferences along with the comparison of different wireless network simulators suitable for LTE

Low latency parallel turbo decoding implementation for future terrestrial broadcasting systems

As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future terrestrial broadcasting (TB) systems. Among all the demands of future TB system, high throughput and low latency are two basic requirements that need to be met. Parallel turbo decoding is a very effective method to reduce the latency and improve the throughput in the decoding stage. In this paper, a parallel turbo decoder is designed and implemented in field-programmable gate array (FPGA). A reverse address generator is proposed to reduce the complexity of interleaver and also the iteration time. A practical method of modulo operation is realized in FPGA which can save computing resources compared with using division operation. The latency of parallel turbo decoder after implementation can be as low as 23.2 us at a clock rate of 250 MHz and the throughput can reach up to 6.92 Gbps

Dynamic reconfiguration technologies based on FPGA in software defined radio system

Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design

A Unified Multi-Functional Dynamic Spectrum Access Framework: Tutorial, Theory and Multi-GHz Wideband Testbed

Dynamic spectrum access is a must-have ingredient for future sensors that are ideally cognitive. The goal of this paper is a tutorial treatment of wideband cognitive radio and radar—a convergence of (1) algorithms survey, (2) hardware platforms survey, (3) challenges for multi-function (radar/communications) multi-GHz front end, (4) compressed sensing for multi-GHz waveforms—revolutionary A/D, (5) machine learning for cognitive radio/radar, (6) quickest detection, and (7) overlay/underlay cognitive radio waveforms. One focus of this paper is to address the multi-GHz front end, which is the challenge for the next-generation cognitive sensors. The unifying theme of this paper is to spell out the convergence for cognitive radio, radar, and anti-jamming. Moore’s law drives the system functions into digital parts. From a system viewpoint, this paper gives the first comprehensive treatment for the functions and the challenges of this multi-function (wideband) system. This paper brings together the inter-disciplinary knowledge

Digital Modulations Using the Universal Software Radio Peripheral

Software defined radios (SDRs) are versatile systems that integrate hardware and software to create a reprogrammable wireless system. Due to the versatility and hardware requirements of a SDR, they are typically expensive and not always affordable for educational institutions. GNU Radio is a free software package that allows users to do signal processing on any computer using python and C++. Using the Universal Software Radio Peripheral (USRP) board in conjunction with a standard personal computer (PC), a RF daughterboard, and the GNU Radio software, we can create a software defined radio that can transmit, receive, and process signals. Because the USRP a personal computer to perform symbol generation, less specialized hardware is needed for the implementation of a software radio, thus reducing the overall system cost. The low cost of a USRP-based SDR enables the implementation of SDRs in laboratory courses, allowing students to learn about digital signal processing along with wireless communication systems. The objective of this senior project is to develop a low-cost SDR that can be used to support student learning of digital wireless communications in a laboratory setting. To demonstrate the capabilities of the SDR, example modulations using BFSK and BASK were developed. In addition, supporting documents like a “quick-start guide” were created to assist in the implementation of SDRs in a digital communications lab. The RFX400 daughterboard was used as a front end with the USRP to test if a college level student could use this hardware with GNU Radio to transmit a modulated signal. The carrier frequencies of these modulated signals were increased to within the bandwidth of the RFX400, 400 to 500 MHz, then these signals were transmitted and successfully received but not with the same clarity as the signal before transmission. Transmitting signals through the air always causes signal degradation, but the number of samples that the USRP uses during reception also affects the quality of the received signal. The USRP and GNU Radio are the ideal hardware and software combination to use by students due to the affordability, versatility, and ease of use

NetFPGA: status, uses, developments, challenges, and evaluation

The constant growth of the Internet, driven by the demand for timely access to data center networks; has meant that the technological platforms necessary to achieve this purpose are outside the current budgets. In this order to make and validate relevant, timely and relevant contributions; it is necessary that a wider community, access to evaluation, experimentation and demonstration environments with specifications that can be compared with existing networking solutions. This article introduces the NetFPGA, which is a platform to develop network hardware for reconfigurable and rapid prototyping. It’s introduces the application areas in high-performance networks, advantages for traffic analysis, packet flow, hardware acceleration, power consumption and parallel processing in real time. Likewise, it presents the advantages of the platform for research, education, innovation, and future trends of this platform. Finally, we present a performance evaluation of the tool called OSNT (Open-Source Network Tester) and shows that OSNT has 95% accuracy of timestamp with resolution of 10ns for the generation of TCP traffic, and 90% efficiency capturing packets at 10Gbps of full line-rate

IREEL: remote experimentation with real protocols and applications over emulated network

This paper presents a novel e-learning platform called IREEL. IREEL is a virtual laboratory allowing students to drive experiments with real Internet applications and end-to-end protocols in the context of networking courses. This platform consists in a remote network emulator offering a set of predefined applications and protocol mechanisms. Experimenters configure and control the emulation and the end-systems behavior in order to perform tests, measurements and observations on protocols or applications operating under controlled specific networking conditions. A set of end-to-end mechanisms, mainly focusing on transport and application level protocols, are currently available. IREEL is scalable and easy to use thanks to an ergonomic web interface

Networked control system with MANET communication and AODV routing

The industries are presently exploring the use of wired and wireless systems for control, automation, and monitoring. The primary benefit of wireless technology is that it reduces the installation cost, in both money and labor terms, as companies already have a significant investment in wiring. The research article presents the work on the analysis of Mobile Ad Hoc Network (MANET) in a wireless real-time communication medium for a Networked Control System (NCS), and determining whether the simulated behavior is significant for a plant or not. The behavior of the MANET is analyzed for Ad-hoc on-demand distance vector routing (AODV) that maintenances communication among 150 nodes for NCS. The simulation is carried out in Network Simulator (NS2) software with different nodes cluster to estimate the network throughput, end-to-end delay, packet delivery ratio (PDR), and control overhead. The benefit of MANET is that it has a fixed topology, which permits flexibility since mobile devices may be used to construct ad-hoc networks anywhere, scalability because more nodes can be added to the network, and minimal operating expenses in that no original infrastructure needs to be developed. AODV routing is a flat routing system that does not require central routing nodes. As the network grows in size, the network can be scaled to meet the network design and configuration requirements. AODV is flexible to support different configurations and topological nodes in dynamic networks because of its versatility. The advantage of such network simulation and routing behavior provides the future direction for the researchers who are working towards the embedded hardware solutions for NCS, as the hardware complexity depends on the delay, throughput, and PDR