Design and implementation of FPGA-based systems - a review

This paper reviews the state of the art of field programmable gate array (FPGA) with the focus on FPGA-based systems. The paper starts with an overview of FPGA in the previous literature, after that starts to get an idea about FPGA programming. FPGA-based neural networks also provided in this paper in order to highlight the best advantage by using FPGA with this type of intelligent systems, and a survey of FPGA-based control systems design with different applications. In this paper, we focus on the main differences between software-based systems with respect to FPGA-based systems, and the main features for FPGA technology and its real-time applications. FPGA-based robotics systems design also provided in this review, finally, the most popular simulation results with FPGA design and implementations are highlighted

Model Based Design and Auto coding of an FPGA Based Satellite Control System

We describe the implementation of a low-power, radiation-tolerant field programmable gate array (FPGA) satellite control system targeted for CubeSats. FPGA based control systems have advantages over microprocessor systems in that they provide parallel and real time processing and can more easily be radiation hardened. They can provide larger computational capability at low powers than a microprocessor. A major drawback has been the inflexibility and difficulty in programming FPGAs relative to the simplicity of using a microprocessor and a real time operating system. Another drawback has been the difficulty in testing the FPGA design without complete hardware. Recently tool chains have been developed by Mathworks that can auto code FPGAs directly from Simulink models. This development process can mitigate difficulties in developing a fully FPGA based satellite control system. Simulink can be used to verify the functionality and performance of the satellite control system as a model of the high level algorithms. The Hardware Description Language (HDL) for the FPGA can be auto generated from the Simulink model. The Simulink model can then be used in a hardware in the loop verification of the FPGA performance. We have used Simulink to model control systems for two different spacecraft subsystems. The first being an Attitude Determination and Control System (ADCS) and the second being a controller for a science payload. The Simulink model of the ADCS allows for testing of the algorithms in a way we can track what is happening form input to output. This allows us to thoroughly understand the implantations of the algorithms and test how data will be transferred between throughout the ADCS using flight commands. These models have been auto coded to HDL and then placed on the FPGAs. We are currently proceeding to a hardware in loop with model to verify that the hardware implementation matches the model. This has allowed the use Simulink as a kind of testing interface for the FPGAs. With the science payload we have done the same kind of hardware in the loop testing with the advantage that the direct connection with Matlab simplifies the calibration process of the instrument. Data from the payload is sent directly back to Simulink which is then analyzed in real-time. We report on the advantages and disadvantages of using FPGA based state-machine verses microprocessor controllers and how this is impacted by modern development tools

A Heterogeneous FPGA/GPU Architecture for Real-Time Data Analysis and Fast Feedback Systems

We propose a versatile and modular approach for a real- time data acquisition and evaluation system for monitoring and feedback control in beam diagnostic and photon sci- ence experiments. Our hybrid architecture is based on an FPGA readout card and GPUs for data processing. To in- crease throughput, lower latencies and reduce overall system strain, the FPGA is able to write data directly into the GPU’s memory. After real-time data analysis the GPU writes back results back to the FPGA for feedback systems or to the CPU host system for subsequent processing. The communication and scheduling processing units are handled transparently by our processing framework which users can customize and extend. Although the system is designed for real-time capability purposes, the modular approach also allows stan- dalone usage for high-speed off-line analysis. We evaluated the performance of our solution measuring both processing times of data analysis algorithms used with beam instrumen- tation detectors as well as transfer times between FPGA and GPU. The latter suggests system throughputs of up to 6 GB/s with latencies down to the microsecond range, thus making it suitable for fast feedback systems

FPGA Based Engine Feedback Control Algorithms

High resolution real time heat release analysis will become increasingly important in the future development of engine control systems. The increased demands on efficiency and emissions will put high demands on future engine control. Future engine concepts, for example the HCCI engine concept might crave cylinder pressure based Closed-Loop Combustion Control (CLCC). The analysis of cylinder pressure is a relatively computationally expensive task that is difficult to implement in existing engine controllers due to the real time demands. This paper describes an approach to obtain such a high speed heat release analysis. The described system could act as a platform for further feedback control experiments. An experimental setup is put together. The heat release algorithm is then developed using MATLAB and SIMULINK. The emerging environment will serve as a prototyping system that can be used for further development of advanced cylinder pressure based feedback control strategies. The performance of the developed algorithm/system is examined in a simulated engine environment. The heart of the system is a Field Programmable Gate Array (FPGA), an FPGA is best described as an reconfigurable Application Specific Integrated Circuit (ASIC). The usage of an FPGA gives the possibility of very high throughput and very low delay time and jitter of the final system. This system could of course also be developed using a normal Commersial Of The Shelf (COTS) processor and a Real Time Operating System (RTOS). The high performance that would be needed to calculate the heat release in the desired time in a multi cylinder engine would however put high demands on the used processor; hence the price of the processor might make the system too expensive, the FPGA describes an alternative approach

AER-based robotic closed-loop control system

Address-Event-Representation (AER) is an asynchronous protocol for transferring the information of spiking neuro-inspired systems. Actually AER systems are able to see, to ear, to process information, and to learn. Regarding to the actuation step, the AER has been used for implementing Central Pattern Generator algorithms, but not for controlling the actuators in a closed-loop spike-based way. In this paper we analyze an AER based model for a real-time neuro-inspired closed-loop control system. We demonstrate it into a differential control system for a two-wheel vehicle using feedback AER information. PFM modulation has been used to power the DC motors of the vehicle and translation into AER of encoder information is also presented for the close-loop. A codesign platform (called AER-Robot), based into a Xilinx Spartan 3 FPGA and an 8051 USB microcontroller, with power stages for four DC motors has been used for the demonstrator.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0

Neuro-inspired system for real-time vision sensor tilt correction

Neuromorphic engineering tries to mimic biological information processing. Address-Event-Representation (AER) is an asynchronous protocol for transferring the information of spiking neuro-inspired systems. Currently AER systems are able sense visual and auditory stimulus, to process information, to learn, to control robots, etc. In this paper we present an AER based layer able to correct in real time the tilt of an AER vision sensor, using a high speed algorithmic mapping layer. A codesign platform (the AER-Robot platform), with a Xilinx Spartan 3 FPGA and an 8051 USB microcontroller, has been used to implement the system. Testing it with the help of the USBAERmini2 board and the jAER software.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-02Ministerio de Ciencia e Innovación TEC2009-10639-C04-0

GPU-based Real-time Triggering in the NA62 Experiment

Over the last few years the GPGPU (General-Purpose computing on Graphics Processing Units) paradigm represented a remarkable development in the world of computing. Computing for High-Energy Physics is no exception: several works have demonstrated the effectiveness of the integration of GPU-based systems in high level trigger of different experiments. On the other hand the use of GPUs in the low level trigger systems, characterized by stringent real-time constraints, such as tight time budget and high throughput, poses several challenges. In this paper we focus on the low level trigger in the CERN NA62 experiment, investigating the use of real-time computing on GPUs in this synchronous system. Our approach aimed at harvesting the GPU computing power to build in real-time refined physics-related trigger primitives for the RICH detector, as the the knowledge of Cerenkov rings parameters allows to build stringent conditions for data selection at trigger level. Latencies of all components of the trigger chain have been analyzed, pointing out that networking is the most critical one. To keep the latency of data transfer task under control, we devised NaNet, an FPGA-based PCIe Network Interface Card (NIC) with GPUDirect capabilities. For the processing task, we developed specific multiple ring trigger algorithms to leverage the parallel architecture of GPUs and increase the processing throughput to keep up with the high event rate. Results obtained during the first months of 2016 NA62 run are presented and discussed

Adaptive Proactive Inhibitory Control for Embedded Real-Time Applications

Psychologists have studied the inhibitory control of voluntary movement for many years. In particular, the countermanding of an impending action has been extensively studied. In this work, we propose a neural mechanism for adaptive inhibitory control in a firing-rate type model based on current findings in animal electrophysiological and human psychophysical experiments. We then implement this model on a field-programmable gate array (FPGA) prototyping system, using dedicated real-time hardware circuitry. Our results show that the FPGA-based implementation can run in real-time while achieving behavioral performance qualitatively suggestive of the animal experiments. Implementing such biological inhibitory control in an embedded device can lead to the development of control systems that may be used in more realistic cognitive robotics or in neural prosthetic systems aiding human movement control

Dynamically reconfigurable management of energy, performance, and accuracy applied to digital signal, image, and video Processing Applications

There is strong interest in the development of dynamically reconfigurable systems that can meet real-time constraints in energy/power-performance-accuracy (EPA/PPA). In this dissertation, I introduce a framework for implementing dynamically reconfigurable digital signal, image, and video processing systems. The basic idea is to first generate a collection of Pareto-optimal realizations in the EPA/PPA space. Dynamic EPA/PPA management is then achieved by selecting the Pareto-optimal implementations that can meet the real-time constraints. The systems are then demonstrated using Dynamic Partial Reconfiguration (DPR) and dynamic frequency control on FPGAs. The framework is demonstrated on: i) a dynamic pixel processor, ii) a dynamically reconfigurable 1-D digital filtering architecture, and iii) a dynamically reconfigurable 2-D separable digital filtering system. Efficient implementations of the pixel processor are based on the use of look-up tables and local-multiplexes to minimize FPGA resources. For the pixel-processor, different realizations are generated based on the number of input bits, the number of cores, the number of output bits, and the frequency of operation. For each parameters combination, there is a different pixel-processor realization. Pareto-optimal realizations are selected based on measurements of energy per frame, PSNR accuracy, and performance in terms of frames per second. Dynamic EPA/PPA management is demonstrated for a sequential list of real-time constraints by selecting optimal realizations and implementing using DPR and dynamic frequency control. Efficient FPGA implementations for the 1-D and 2-D FIR filters are based on the use a distributed arithmetic technique. Different realizations are generated by varying the number of coefficients, coefficient bitwidth, and output bitwidth. Pareto-optimal realizations are selected in the EPA space. Dynamic EPA management is demonstrated on the application of real-time EPA constraints on a digital video. The results suggest that the general framework can be applied to a variety of digital signal, image, and video processing systems. It is based on the use of offline-processing that is used to determine the Pareto-optimal realizations. Real-time constraints are met by selecting Pareto-optimal realizations pre-loaded in memory that are then implemented efficiently using DPR and/or dynamic frequency control