Design of an oximeter based on LED-LED configuration and FPGA technology

sensor

Electrocardiogram (ECG/EKG) using FPGA

FPGAs (Field Programmable Gate Arrays) are finding wide acceptance in medical systems for their ability for rapid prototyping of a concept that requires hardware/software co-design, for performing custom processing in parallel at high data rates and be programmed in the field after manufacturing. Based on the market demand, the FPGA design can be changed and no new hardware needs to be purchased as was the case with ASICs (Application Specific Integrated Circuit) and CPLDs (Complex Programmable Logic Device). Medical companies can now move over to FPGAs saving cost and delivering highly-efficient upgradable systems. ECG (Electrocardiogram) is considered to be a must have feature for a medical diagnostic imaging system. This project attempts at implementing ECG heart-rate computation in an FPGA. This project gave me exposure to hardware engineering, learning about the low level chips like Atmel UC3A3256 micro-controller on an Atmel EVK1105 board which is used as a simulator for generating the ECG signal, the operational amplifiers for amplifying and level-shifting the ECG signal, the A/D converter chip for analog to digital conversion of the ECG signal, the internal workings of FPGA, how different hardware components communicate with each other on the system and finally some signal processing to calculate the heart rate value from the ECG signal

LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing

LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.Peer ReviewedPostprint (author's final draft

An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links

Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02/01Ministerio de Economía y Competitividad TEC2012-37868-C04-02/01Junta de Andalucía TIC-6091Ministerio de Economía y Competitividad PRI-PIMCHI-2011-076

Design of a "Digital Atlas Vme Electronics" (DAVE) Module

ATLAS-SCT has developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' ("DAVE"). The unit is designed to provide a versatile array of interface and logic resources, including a large FPGA. It interfaces to both VME bus and USB hosts. DAVE aims to provide exact ATLAS CTP (ATLAS Central Trigger Processor) functionality, with random trigger, simple and complex deadtime, ECR (Event Counter Reset), BCR (Bunch Counter Reset) etc. being generated to give exactly the same conditions in standalone running as experienced in combined runs. DAVE provides additional hardware and a large amount of free firmware resource to allow users to add or change functionality. The combination of the large number of individually programmable inputs and outputs in various formats, with very large external RAM and other components all connected to the FPGA, also makes DAVE a powerful and versatile FPGA utility cardComment: 8 pages, 4 figures, TWEPP-2011; E-mail: [email protected]

A Large-Scale FPGA-Based Trigger and Dead-Time Free DAQ System for the Kaos Spectrometer at MAMI

The Kaos spectrometer is maintained by the A1 collaboration at the Mainz Microtron MAMI with a focus on the study of (e,e'K^+) coincidence reactions. For its electron-arm two vertical planes of fiber arrays, each comprising approximately 10 000 fibers, are operated close to zero degree scattering angle and in close proximity to the electron beam. A nearly dead-time free DAQ system to acquire timing and tracking information has been installed for this spectrometer arm. The signals of 144 multi-anode photomultipliers are collected by 96-channel front-end boards, digitized by double-threshold discriminators and the signal time is picked up by state-of-the-art F1 time-to-digital converter chips. In order to minimize background rates a sophisticated trigger logic was implemented in newly developed Vuprom modules. The trigger performs noise suppression, signal cluster finding, particle tracking, and coincidence timing, and can be expanded for kinematical matching (e'K^+) coincidences. The full system was designed to process more than 4 000 read-out channels and to cope with the high electron flux in the spectrometer and the high count rate requirement of the detectors. It was successfully in-beam tested at MAMI in 2009.Comment: Contributed to 17th IEEE Real Time Conference (RT10), Lisbon, 24-28 May 201