A Combined First Principles and Kinetic Monte Carlo study of Polyoxometalate based Molecular Memory Devices

In this paper, we combine Density Functional Theory with Kinetic Monte Carlo methodology to study the fundamental transport properties of a type of polyoxometalate (POM) and its behaviour in a potential flash memory device. DFT simulations on POM molecular junctions helps us demonstrate the link between underlying electronic structure of the molecule and its transport properties. Furthermore, we show how various electrode-molecule contact configurations determine the electron transport through the POM. Also, our work reveals that the orientation of the molecule to the electrodes plays a key role in the transport properties of the junction. With Kinetic Monte Carlo we extend this investigation by simulating the retention time of a POM-based flash memory device. Our results show that a POM based flash memory could potentially show multi-bit storage and retain charge for up to 10 years

Memristive Non-Volatile Memory Based on Graphene Materials

Resistive random access memory (RRAM), which is considered as one of the most promising next-generation non-volatile memory (NVM) devices and a representative of memristor technologies, demonstrated great potential in acting as an artificial synapse in the industry of neuromorphic systems and artificial intelligence (AI), due its advantages such as fast operation speed, low power consumption, and high device density. Graphene and related materials (GRMs), especially graphene oxide (GO), acting as active materials for RRAM devices, are considered as a promising alternative to other materials including metal oxides and perovskite materials. Herein, an overview of GRM-based RRAM devices is provided, with discussion about the properties of GRMs, main operation mechanisms for resistive switching (RS) behavior, figure of merit (FoM) summary, and prospect extension of GRM-based RRAM devices. With excellent physical and chemical advantages like intrinsic Young’s modulus (1.0 TPa), good tensile strength (130 GPa), excellent carrier mobility (2.0 × 105 cm2∙V−1∙s−1), and high thermal (5000 Wm−1∙K−1) and superior electrical conductivity (1.0 × 106 S∙m−1), GRMs can act as electrodes and resistive switching media in RRAM devices. In addition, the GRM-based interface between electrode and dielectric can have an effect on atomic diffusion limitation in dielectric and surface effect suppression. Immense amounts of concrete research indicate that GRMs might play a significant role in promoting the large-scale commercialization possibility of RRAM devices

In-memory computing with emerging memory devices: Status and outlook

Supporting data for "In-memory computing with emerging memory devices: status and outlook", submitted to APL Machine Learning

Caractérisation, mécanismes et applications mémoire des transistors avancés sur SOI

Ce travail présente les principaux résultats obtenus avec une large gamme de dispositifs SOI avancés, candidats très prometteurs pour les futurs générations de transistors MOSFETs. Leurs propriétés électriques ont été analysées par des mesures systématiques, agrémentées par des modèles analytiques et/ou des simulations numériques. Nous avons également proposé une utilisation originale de dispositifs FinFETs fabriqués sur ONO enterré en fonctionnalisant le ONO à des fins d'application mémoire non volatile, volatile et unifiées. Après une introduction sur l'état de l'art des dispositifs avancés en technologie SOI, le deuxième chapitre a été consacré à la caractérisation détaillée des propriétés de dispositifs SOI planaires ultra- mince (épaisseur en dessous de 7 nm) et multi-grille. Nous avons montré l excellent contrôle électrostatique par la grille dans les transistors très courts ainsi que des effets intéressants de transport et de couplage. Une approche similaire a été utilisée pour étudier et comparer des dispositifs FinFETs à double grille et triple grille. Nous avons démontré que la configuration FinFET double grille améliore le couplage avec la grille arrière, phénomène important pour des applications à tension de seuil multiple. Nous avons proposé des modèles originaux expliquant l'effet de couplage 3D et le comportement de la mobilité dans des TFTs nanocristallin ZnO. Nos résultats ont souligné les similitudes et les différences entre les transistors SOI et à base de ZnO. Des mesures à basse température et de nouvelles méthodes d'extraction ont permis d'établir que la mobilité dans le ZnO et la qualité de l'interface ZnO/SiO2 sont remarquables. Cet état de fait ouvre des perspectives intéressantes pour l'utilisation de ce type de matériaux aux applications innovantes de l'électronique flexible. Dans le troisième chapitre, nous nous sommes concentrés sur le comportement de la mobilité dans les dispositifs SOI planaires et FinFET en effectuant des mesures de magnétorésistance à basse température. Nous avons mis en évidence expérimentalement un comportement de mobilité inhabituel (multi-branche) obtenu lorsque deux ou plusieurs canaux coexistent et interagissent. Un autre résultat original concerne l existence et l interprétation de la magnétorésistance géométrique dans les FinFETs.L'utilisation de FinFETs fabriqués sur ONO enterré en tant que mémoire non volatile flash a été proposée dans le quatrième chapitre. Deux mécanismes d'injection de charge ont été étudiés systématiquement. En plus de la démonstration de la pertinence de ce type mémoire en termes de performances (rétention, marge de détection), nous avons mis en évidence un comportement inattendu : l amélioration de la marge de détection pour des dispositifs à canaux courts. Notre concept innovant de FinFlash sur ONO enterré présente plusieurs avantages: (i) opération double-bit et (ii) séparation de la grille de stockage et de l'interface de lecture augmentant la fiabilité et autorisant une miniaturisation plus poussée que des Finflash conventionnels avec grille ONO.Dans le dernier chapitre, nous avons exploré le concept de mémoire unifiée, en combinant les opérations non volatiles et 1T-DRAM par le biais des FinFETs sur ONO enterré. Comme escompté pour les mémoires dites unifiées, le courant transitoire en mode 1T-DRAM dépend des charges non volatiles stockées dans le ONO. D'autre part, nous avons montré que les charges piégées dans le nitrure ne sont pas perturbées par les opérations de programmation et lecture de la 1T-DRAM. Les performances de cette mémoire unifiée multi-bits sont prometteuses et pourront être considérablement améliorées par optimisation technologique de ce dispositif.The evolution of electronic systems and portable devices requires innovation in both circuit design and transistor architecture. During last fifty years, the main issue in MOS transistor has been the gate length scaling down. The reduction of power consumption together with the co-integration of different functions is a more recent avenue. In bulk-Si planar technology, device shrinking seems to arrive at the end due to the multiplication of parasitic effects. The relay has been taken by novel SOI-like device architectures. In this perspective, this manuscript presents the main achievements of our work obtained with a variety of advanced fully depleted SOI MOSFETs, which are very promising candidates for next generation MOSFETs. Their electrical properties have been analyzed by systematic measurements and clarified by analytical models and/or simulations. Ultimately, appropriate applications have been proposed based on their beneficial features.In the first chapter, we briefly addressed the short-channel effects and the diverse technologies to improve device performance. The second chapter was dedicated to the detailed characterization and interesting properties of SOI devices. We have demonstrated excellent gate control and high performance in ultra-thin FD SOI MOSFET. The SCEs are efficiently suppressed by decreasing the body thickness below 7 nm. We have investigated the transport and electrostatic properties as well as the coupling mechanisms. The strong impact of body thickness and temperature range has been outlined. A similar approach was used to investigate and compare vertical double-gate and triple-gate FinFETs. DG FinFETs show enhanced coupling to back-gate bias which is applicable and suitable for dynamic threshold voltage tuning. We have proposed original models explaining the 3D coupling effect in FinFETs and the mobility behavior in ZnO TFTs. Our results pointed on the similarities and differences in SOI and ZnO transistors. According to our low-temperature measurements and new promoted extraction methods, the mobility in ZnO and the quality of ZnO/SiO2 interface are respectable, enabling innovating applications in flexible, transparent and power electronics. In the third chapter, we focused on the mobility behavior in planar SOI and FinFET devices by performing low-temperature magnetoresistance measurements. Unusual mobility curve with multi-branch aspect were obtained when two or more channels coexist and interplay. Another original result in the existence of the geometrical magnetoresistance in triple-gate and even double-gate FinFETs.The operation of a flash memory in FinFETs with ONO buried layer was explored in the forth chapter. Two charge injection mechanisms were proposed and systematically investigated. We have discussed the role of device geometry and temperature. Our novel ONO FinFlash concept has several distinct advantages: double-bit operation, separation of storage medium and reading interface, reliability and scalability. In the final chapter, we explored the avenue of unified memory, by combining nonvolatile and 1T-DRAM operations in a single transistor. The key result is that the transient current, relevant for 1T-DRAM operation, depends on the nonvolatile charges stored in the nitride buried layer. On the other hand, the trapped charges are not disturbed by the 1T-DRAM operation. Our experimental data offers the proof-of-concept for such advanced memory. The performance of the unified/multi-bit memory is already decent but will greatly improve in the coming years by processing dedicated devices.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Optimisation du procédé de réalisation pour l'intégration séquentielle 3D des transistors CMOS FDSOI

L activation à basse température est prometteuse pour l intégration 3D séquentielle où lebudget thermique du transistor supérieur est limité (<650 C) pour ne pas dégrader letransistor inférieur, mais aussi dans le cas d une intégration planaire afin d atteindre des EOTultra fines et de contrôler le travail de sortie de la grille sans recourir à une intégration de type gate-last . Dans ce travail, l activation par recroissance en phase solide (SPER) a étéétudiée afin de réduire le budget thermique de l activation des dopants.L activation à basse température présente plusieurs inconvénients. Les travauxprécédents montrent que les fuites de jonctions sont plus importantes dans ces dispositifs.Ensuite, des fortes désactivations de dopants ont été observées. Troisièmement, la faiblediffusion des dopants rend difficile la connexion des jonctions source et drain avec le canal.Dans ce travail, il est montré que dans un transistor FDSOI, l augmentation des fuites dejonctions et la désactivation du Bore peuvent être évités grâce à la présence de l oxyde enterré.De plus les conditions d implantation ont été optimisées et les transistors activés à650 C atteignent les performances des transistors de référence.Low temperature (LT) process is gaining interest in the frame of 3D sequentialintegration where limited thermal budget (<650 C) is needed for top FET to preserve bottomFET from any degradation and also in the standard planar integration for achieving ultra-thinEOT and work function control with high-k metal gate without gate-last integration scheme.In this work, LT Solid Phase Epitaxial Regrowth (SPER) has been investigated for reducingthe most critical thermal budget which is dopant activation.From previous works, LT activated devices face several challenges: First, higher junctionleakage limits their application to high performance devices. Secondly, strong deactivation ofthe metastable activated dopants was observed with post anneals. Thirdly, the dopant weakdiffusion makes it difficult to connect the channel with S/D.In this work, it is shown that the use of FDSOI enables to overcome junction leakage andBoron deactivation issues thanks to the defect cutting off and sinking effect of buried oxide.As a consequence, dopant deactivation in FDSOI devices is no longer an issue. Finally,implants conditions of LT transistors have been optimized to reach similar performance thanits standard high temperature counterparts.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Low-Temperature Technologies and Applications

This book on low-temperature technology is a notable collection of different aspects of the technology and its application in varieties of research and practical engineering fields. It contains, sterilization and preservation techniques and their engineering and scientific characteristics. Ultra-low temperature refrigeration, the refrigerants, applications, and economic aspects are highlighted in this issue. The readers will find the low temperature, and vacuum systems for industrial applications. This book has given attention to global energy resources, conservation of energy, and alternative sources of energy for the application of low-temperature technologies

신경계 모방 시스템을 위한 실리콘 기반 시냅스 모방 트랜지스터

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 박병국.Current computing systems based on the von Neumann architecture suffer from the fact that serious leakage current issues have risen up in nanoscale devices. Neuromorphic computing system has been believed to solve fundamental challenges in current computing system by mimicking a biological nervous system, especially in terms of parallel signal processing. Synaptic devices are considered as the one of the most important parts of neuromorphic systems because a biological synapse is thought to control signal transmissions and memory effects in our nervous system. However, the memristor, one of the strongest candidates for an artificial synapse, requires additional switching parts in order to transfer and receive signals using the same electrode, leading to extra overheads that may compromise the advantages of massive parallelism inherent in neuromorphic systems. In this dissertation, a silicon-based synaptic transistor with asymmetric dual-gate structure is investigated. The structural feature enables the synaptic transistors to interact with both pre- and post-synaptic neuron circuits directly. A TCAD device simulator and a circuit simulator are used to verify its synaptic learning properties and study its mechanism fundamentally. After verifying all the fabrication flow using a process simulator, the synaptic transistors are fabricated through process techniques including two-step CMP processes. The electrical and synaptic characteristics of the fabricated devices are measured with a semiconductor parameter analyzer, and a device model is created based on the measured data. Furthermore, spiking neural network composed of them is verified systematically using the device model. From the simulation study and electrical measurement, synaptic learning rules are observed in the synaptic transistors including the transition from short-term to long-term memory and spike-timing dependent plasticity. In addition, the spiking neural network composed of the synaptic transistors boasted its ability of pattern recognition using MNIST data set. The total recognition accuracy of the hardware-based neural network system having 784 input nodes and 10 output nodes is improved to nearly 70% by adding inhibitory synapses. These results indicate that the synaptic transistor studied in this dissertation can be used as a synaptic device in neuromorphic systems thanks to its direct connectability with neuron circuits and synaptic learning properties.Chapter 1. Introduction 1 1.1. Fundamental Challenges in Current Computing System 1 1.2. Neurobiological Background 4 1.2.1. Synaptic Transmission 4 1.2.2. Short-Tem and Long-Term Memory 7 1.2.3. Spike-Timing Dependent Plasiticity 9 1.3. Neuromorphic Computing 12 1.4. Outline of the Dissertation 17 Chapter 2. Silicon-Based Synaptic Transistor 18 2.1. Device Configuration 18 2.2. Device Simulation Study 20 2.2.1. Transition from Short-Term to Long-Term Memory 21 2.2.2. Spike-Timing Dependent Plasticity Characteristics 28 2.3. Circuit Simulation Study 30 Chapter 3. Device Fabrication 34 3.1. Process Design and Fabrication Flow 34 3.2. Experimental Results 41 3.2.1. Deposition of Hard Mask and Patterning 41 3.2.2. Formation of G1 through CMP 44 3.2.3. Removal of Hard Mask 46 3.2.4. Fin Channel Formation Using Sidewall Spacer 48 3.2.5. Gate Splitting through CMP and Etchback Processes 50 Chapter 4. Device Characteristics 52 4.1. Field-Effect Transistor Characteristics 52 4.2. Synaptic Learning Properties 54 4.2.1. Transition from Short-Term to Long-Term Memory 54 4.2.2. Spike-Timing Dependent Plasticity Characteristics 58 Chapter 5. System Level Simulation 64 5.1. Hardware-Based Spiking Neural Network 64 5.2. Transferred Synaptic Weights from ANN Using ReLU 69 5.3. Addition of Inhibitory Synapse Part 73 Chapter 6. Conclusion 78 6.1. Review of Overall Work 78 6.2. Future Work 80 Appendix A. Multi-Threshold Voltages in Ultra Thin Body Devices by Asymmetric Dual-Gate Structure 82 Appendix B. Asymmetric Dual-Gate-Structured 1-T DRAM Cell for Retention Characteristics Improvement 90 Appendix C. A Single Memory Cell with Voltaile and Non-Volatile Memory Functions 101 Bibliography 109 Abstract in Korean 133Docto

Influence of the contact geometry and counterions on the current flow and charge transfer in polyoxometalate molecular junctions: a density functional theory study

Polyoxometalates (POMs) are promising candidates for molecular electronic applications because (1) they are inorganic molecules, which have better CMOS compatibility compared to organic molecules; (2) they are easily synthesized in a one-pot reaction from metal oxides (MOx) (where the metal M can be, e.g., W, V, or Mo, and x is an integer between 4 and 7); (3) POMs can self-assemble to form various shapes and configurations, and thus the chemical synthesis can be tailored for specific device performance; and (4) they are redox-active with multiple states that have a very low voltage switching between polarized states. However, a deep understanding is required if we are to make commercial molecular devices a reality. Simulation and modeling are the most time efficient and cost-effective methods to evaluate a potential device performance. Here, we use density functional theory in combination with nonequilibrium Green’s function to study the transport properties of [W18O54(SO3)2]4–, a POM cluster, in a variety of molecular junction configurations. Our calculations reveal that the transport profile not only is linked to the electronic structure of the molecule but also is influenced by contact geometry and presence of ions. More specifically, the contact geometry and the number of bonds between the POM and the electrodes determine the current flow. Hence, strong and reproducible contact between the leads and the molecule is mandatory to establish a reliable fabrication process. Moreover, although often ignored, our simulations show that the charge balancing counterions activate the conductance channels intrinsic to the molecule, leading to a dramatic increase in the computed current at low bias. Therefore, the role of these counterions cannot be ignored when molecular based devices are fabricated. In summary, this work shows that the current transport in POM junctions is determined by not only the contact geometry between the molecule and the electrode but also the presence of ions around the molecule. This significantly impacts the transport properties in such nanoscale molecular electronic devices

양성 피드백 전계 효과 트랜지스터를 활용한 저전력 시냅스 소자

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 박병국.신경망 모방 시스템은 폰 노이만 구조의 계산 시스템이 가지는 약점인 복잡한 인식 문제를 해결과 에너지 소비의 효율성의 가능성으로 수년간 많은 분야에서 연구되고 있고 일부는 상용화 단계에까지 이르렀다. 이 신경 모방 시스템은 시냅스 모방 소자와 뉴런 회로로 이루어 지는데 시냅스 모방 소자는 신호전달과 기억 기능을 담당하고 있다. 시냅스는 전체 신경모방 시스템에서 가장 큰 부분을 차지 한다. 따라서 시스템내 대부분의 전력 소비가 시냅스 부분에서 일어나게 되므로 저전력 구현이 필수적인 요소다. 이런 이유로 저전력 소자에 특화된 소자인 터널 전계 효과 트랜지스터 (TFET), 네거티브 커페시터 전계효과 트랜지스터 (NCFET), 강유전계 효과 트랜지스터 (FeFET) 및 피드백 전계 효과 트랜지스터 (FBFET) 등이 연구되고 있다. 이런 다양한 소자중에 현재의 상보형 금속-산화물-반도체 (CMOS) 공정을 그대로 사용할 수 있는 피드백 전계 효과 트랜지스터는 뉴런 회로와 동시에 제작이 필요한 신경망 모방 시스템에서 대량 생산 가능성에 있어서 매우 유리하다. 본 논문에서는 이 피드백 전계 효과 트랜지스터를 기반으로 하고 NAND 플래시 메모리 구조에서 사용하는 파울러 노르다임 터널링(Fowler-Nordheim tunneling)을 방식으로 차치 트랩 층에 시냅스 소자의 가중치를 기억하는 방식의 시냅스 장치를 제안하고 있다. 해당 소자의 저전력 특성과 구동 방법을 테크놀로지 컴퓨터 지원 설계 (TCAD) 시뮬레이션을 사용하여 유효성을 확인 하였고, 서울대 반도체 공동 연구소 (ISRC) 의 CMOS 공정을 사용하여 소자를 제작하였고 전기적 특성 측정을 통해 제안된 방법을 확인 및 검증 하였다.The neuromorphic system has been widely used and commercialized in many fields in recent years due to its potential for complex problem solving and low energy consumption. The basic elements of this neuromorphic system are synapse and neuron circuit, in which synapse research is focused on emerging electronic devices such as resistive change memory (RRAM), phase-change memory (PCRAM), magnetoresistive random-access memory (MRAM), and FET-based devices. Synapse is responsible for the memory function of the neuromorphic system, that is, the current sum quantization with the specific weight value. and the neuron is responsible for integrating signals that have passed through the synapse and transmitting information to the next synapse. Since the synapse element is the largest portion of the whole system, It consumes most of the power of the entire system. So low power implementation is essential for the synapse device. In order to reduce power consumption, it is necessary to lower the off-current leakage and operate on low voltage. To overcome the limitation of MOSFETs in terms of ION/IOFF ratio, small sub-threshold swing and power consumption, various devices such as a tunneling field-effect transistor (TFET), negative capacitor field-effect transistor (NCFET), ferroelectric field-effect transistor (FeFET), and feedback field-effect transistor (FBFET) have been studied. Another important factor in synapse devices is the cost aspect. The deep learning technology that made Alpha-go exist is also an expensive system. As we can see from the coexistence of supercomputers and personal computers in the past, the development of low-cost chips that can be used by individuals, in the end, is inevitable. Because a CMOS compatible process must be possible since the neuron circuit is needed to fabricate at the same time, which helps to ensure mass productivity. FET-based devices are CMOS process compatible, which is suitable for the mass production environment. A positive FBFET (Feedback Field Effect Transistor) device has a very low sub-threshold current, SS (subthreshold swing) performance, and ION/IOFF ratio at the low operating voltage. We are proposing the synaptic device with a positive FBFET with a storage layer. From the simulation study, the operation method is studied for the weight modulation of the synaptic device and electrical measurement confirms accumulated charge change by program and erase condition each. These results for the synaptic transistor in this dissertation can be one of the candidates in low power neuromorphic systems.1 Introduction 1 1.1 Limitation of von Neumann Architecture computing 1 1.2 Biological Synapse 3 1.3 Spiking Neural Network (SNN) 5 1.4 Requirements of synaptic device 7 1.5 Advantage of Feedback Field-effect transistor (FBFET) 9 1.6 Outline of the Dissertation 10 2 Positive Feedback FET with storage layer 11 2.1 Normal operation Principle of FBFET 14 2.2 Operation Mechanism by Drain Input Pulse 16 2.3 Weight Modulation Mechanism 20 2.4 TCAD Simulation Result for Weighted Sum 23 2.5 TCAD Simulation Result for Program and Erase 28 2.6 Array structure and Inhibition scheme 31 3 Fabrication and Measurement 36 3.1 Fabrication process of FBFET synapse 37 3.2 Measurement result 41 3.3 Hysteresis Reduction 49 3.4 Temperature Compensation method 53 4 Modeling and High level simulation 56 4.1 Compact modeling for SPICE 56 4.2 SPICE simulation for VMM 60 5 Conclusion 64 5.1 Review of Overall Work 64 5.2 Future work 65 Abstract (In Korean) 75Docto

Investigation of Multiple-valued Logic Technologies for Beyond-binary Era

Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore’s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. In this review article, different technologies for Multiple-valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies, and (ii) availability of effective synthesis techniques. This review of different technologies for the MVL system is intended to perform a comprehensive investigation of various MVL technologies and a comparative analysis of the feasible approaches to implement MVL devices, especially ternary logic