Perspective of buried oxide thickness variation on triple metal-gate (TMG) recessed-S/D FD-SOI MOSFET

Recently, Fully-Depleted Silicon on Insulator (FD-SOI) MOSFETs have been accepted as a favourable technology beyond nanometer nodes, and the technique of Recessed-Source/Drain (Re-S/D) has made it more immune in regards of various performance factors. However, the proper selection of Buried-Oxide (BOX) thickness is one of the major challenges in the design of FD-SOI based MOS devices in order to suppress the drain electric penetrations across the BOX interface efficiently. In this work, the effect of BOX thickness on the performance of TMG Re-S/D FD-SOI MOSFET has been presented at 60 nm gate length. The perspective of BOX thickness variation has been analysed on the basis of its surface potential profile and the extraction of the threshold voltage by performing two-dimensional numerical simulations. Moreover, to verify the short channel immunity, the impact of gate length scaling has also been discussed. It is found that the device attains two step-up potential profile with suppressed short channel effects. The outcomes reveal that the Drain Induced Barrier Lowering (DIBL) values are lower among conventional SOI MOSFETs. The device has been designed and simulated by using 2D numerical ATLAS Silvaco TCAD simulator

Monolithic Pixel Sensors in Deep-Submicron SOI Technology

Monolithic pixel sensors for charged particle detection and imaging applications have been designed and fabricated using commercially available, deep-submicron Silicon-On-Insulator (SOI) processes, which insulate a thin layer of integrated full CMOS electronics from a high-resistivity substrate by means of a buried oxide. The substrate is contacted from the electronics layer through vias etched in the buried oxide, allowing pixel implanting and reverse biasing. This paper summarizes the performances achieved with a first prototype manufactured in the OKI 0.15 micrometer FD-SOI process, featuring analog and digital pixels on a 10 micrometer pitch. The design and preliminary results on the analog section of a second prototype manufactured in the OKI 0.20 micrometer FD-SOI process are briefly discussed.Comment: Proceedings of the PIXEL 2008 International Workshop, FNAL, Batavia, IL, 23-26 September 2008. Submitted to JINST - Journal of Instrumentatio

Characterizationof FD-SOI transistor

In this project, measurements have been made on FD-SOI transistors, fabricated by CEA-LETI, to carry out a characterization of these devices, since they are very new and need to be studied. This work has focused on characterizing the aging mechanism of the devices and the observed RTN. To characterize the aging mechanism and variability of the samples based on the applied cycles, the measurements have been made by applying constant stress voltages (CVS) directly to the device with a wafer prove station and a semiconductor parameter analyzer (SPA). To observe TN, different electrical procedures have been studied, controlling the different parameters during the measurements.En aquest projecte s'han realitzat mesures en transistors FD-SOI, fabricats per CEA-LETI, per tal de dur a terme una caracterització d'aquests dispositius, ja que són molt nous i necessiten de ser estudiats. Aquest treball s'ha centrat en caracteritzar l'envelliment dels dispositius i el RTN observat. Per a caracteritzar l'envelliment i la variabilitat de les mostres en funció dels cicles aplicats, les mesures s'han realitzat aplicant tensions d'estrés constant (CVS) directament al dispositiu amb una taula de puntes i un analitzador de paràmetres de semiconductors (SPA). Per tal d'observar RTN s'han estudiat diferents procediments elèctrics, controlant els diferents paràmetres durant les mesures.En este proyecto se han realizado medidas en transistores FD-SOI, fabricados por CEA-LETI, para llevar a cabo una caracterización de estos dispositivos, puesto que son muy nuevos y necesitan de ser estudiados. Este trabajo se ha centrado en caracterizar los mecanismos de envejecimiento de los dispositivos y el RTN observado. Para caracterizar el envejecimiento y la variabilidad de las muestras en función de los ciclos aplicados, las medidas se han realizado aplicando tensiones de estrés constante (CVS) directamente al dispositivo con una tabla de puntas y un analizador de parámetros de semiconductores (SPA). Para observar RTN se han estudiado diferentes procedimientos eléctricos, controlando los diferentes parámetros durante las medidas

Approche industrielle aux boîtes quantiques dans des dispositifs de silicium sur isolant complètement déplété pour applications en information quantique

La mise en oeuvre des qubits de spin électronique à base de boîtes quantiques réalisés en utilisant une technologie avancée de métal-oxyde-semiconducteur complémentaire (en anglais: CMOS ou Complementary Metal-Oxide-Semiconductor) fonctionnant à des températures cryogéniques permet d’envisager la fabrication industrielle reproductible et à haut rendement de systèmes de qubits de spin à grande échelle. Le développement d’une architecture de boîtes quantiques à base de silicium fabriquées en utilisant exclusivement des techniques de fabrication industrielle CMOS constitue une étape majeure dans cette direction. Dans cette thèse, le potentiel de la technologie UTBB (en anglais: Ultra-Thin Body and Buried oxide) silicium sur isolant complétement déplété (en anglais: FD-SOI ou Fully Depleted Silicon-On-Insulator) 28 nm de STMicroelectronics (Crolles, France) a été étudié pour la mise en oeuvre de boîtes quantiques bien définies, capables de réaliser des systèmes de qubit de spin. Dans ce contexte, des mesures d’effet Hall ont été réalisées sur des microstructures FD-SOI à 4.2 K afin de déterminer la qualité du noeud technologique pour les applications de boîtes quantiques. De plus, un flot du processus d’intégration, optimisé pour la mise en oeuvre de dispositifs quantiques utilisant exclusivement des méthodes de fonderie de silicium pour la production de masse est présenté, en se concentrant sur la réduction des risques de fabrication et des délais d’exécution globaux. Enfin, deux géométries différentes de dispositifs à boîtes quantiques FD-SOI de 28nm ont été conçues et leurs performances ont été étudiées à 1.4 K. Dans le cadre d’une collaboration entre Nanoacademic Technologies, Institut quantique et STMicroelectronics, un modèle QTCAD (en anglais: Quantum Technology Computer-Aided Design) en 3D a été développé pour la modélisation de dispositifs à boîtes quantiques FD-SOI. Ainsi, en complément de la caractérisation expérimentale des structures de test via des mesures de transport et de spectroscopie de blocage de Coulomb, leur performance est modélisée et analysée à l’aide du logiciel QTCAD. Les résultats présentés ici démontrent les avantages de la technologie FD-SOI par rapport à d’autres approches pour les applications de calcul quantique, ainsi que les limites identifiées du noeud 28 nm dans ce contexte. Ce travail ouvre la voie à la mise en oeuvre des nouvelles générations de dispositifs à boîtes quantiques FD-SOI basées sur des noeuds technologiques inférieurs.Abstract: Electron spin qubits based on quantum dots implemented using advanced Complementary Metal-Oxide-Semiconductor (CMOS) technology functional at cryogenic temperatures promise to enable reproducible high-yield industrial manufacturing of large-scale spin qubit systems. A milestone in this direction is to develop a silicon-based quantum dot structure fabricated using exclusively CMOS industrial manufacturing techniques. In this thesis, the potential of the industry-standard process 28 nm Ultra-Thin Body and Buried oxide (UTBB) Fully Depleted Silicon-On-Insulator (FD-SOI) technology of STMicroelectronics (Crolles, France) was investigated for the implementation of well-defined quantum dots capable to realize spin qubit systems. In this context, Hall effect measurements were performed on FD-SOI microstructures at 4.2 K to determine the quality of the technology node for quantum dot applications. Moreover, an optimized integration process flow for the implementation of quantum devices, using exclusively mass-production silicon-foundry methods is presented, focusing on reducing manufacturing risks and overall turnaround times. Finally, two different geometries of 28 nm FD-SOI quantum dot devices were conceived, and their performance was studied at 1.4 K. In the framework of a collaboration between Nanoacademic Technologies, Institut quantique, and STMicroelectronics, a 3D Quantum Technology Computer-Aided Design (QTCAD) model was developed for FD-SOI quantum dot device modeling. Therefore, along with the experimental characterization of the test structures via transport and Coulomb blockade spectroscopy measurements, their performance is modeled and analyzed using the QTCAD software. The results reported here demonstrate the advantages of the FD-SOI technology over other approaches for quantum computing applications, as well as the identified limitations of the 28 nm node in this context. This work paves the way for the implementation of the next generations of FD-SOI quantum dot devices based on lower technology nodes

Atlas simulation based study of recessed source/drain SOI mosfets

Front gate and back gate threshold voltage, potential distributions and sub threshold swing of recessed source/drain ultra-thin body silicon on insulator mosfets are simulated and analyzed in a vivid manner with extreme meticulousness. Analysis and comparative study of the electrical characteristics of Re s/d UTB SOI mosfets with that of conventional FD SOI mosfets has been done. Structures of conventional soi mosfet and Re s/d mosfets is simulated with the help of software like ATLAS

Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits

International audienceAmong all means to attack a security dedicated circuit, fault injection by means of laser illumination is a very efficient one. The laser beam creates electrons/holes pairs along its way through the silicon. The collection of these charges creates a transient current and thus may induce a fault in the circuit. Nevertheless the collection efficiency depends on various parameters including the technology used to implement the circuit. Here, up-to-date Bulk and Fully Depleted Silicon on Insulator (FD-SOI) 28nm technologies are compared in terms of sensitivity against laser injection. It comes out that FD-SOI structures show less sensitivity to laser injection and thus should be further explored for security dedicated circuits implementations