Lateral Power Mosfets Hardened Against Single Event Radiation Effects

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metric

Development, fabrication, and characterization of a vertical-diffused MOS process for power RF applications

High power radio frequency (RF) applications have become important because of a growing demand from the wireless market. With their superior switching speed, power Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) have become one of the well-known technologies used in high power RF systems. The primary focus of this thesis work was the development, fabrication, and characterization of discrete Verticaldrain lateral-Diffused MOS (VDMOS) power transistors using an interdigitated source/gate design. Several types of high power devices were also presented for comparison to the VDMOS structure. This thesis describes the overall purpose and the objectives of the proposed project, and provides the methodology used to complete these objectives. This project supports a new development initiative of the project sponsor, Spectrum Devices, Inc., who has been working with RIT in power bipolar technologies over the last two years. The process steps to create a 50 V power VDMOS transistor structure were designed using Silvaco ATHENA (SUPREM-IV) process simulation. Typical power VDMOS transistor fabrication steps were used as a starting point with modifications to include Faraday and UIS implant steps to address certain parasitic effects. The Faraday shield implant was performed to shift the parasitic gate- field capacitance over to the input side of the device, which should dramatically improve the frequency response of the device. The UIS implant was used to reduce the parasitic BJT of a power VDMOS transistor. The implementation of the proposed structure also eliminated the need for an added masking operation for each implant step, and kept the structure self- aligned to the gate stack. This eliminated potential overlay tolerances and error that may be encountered in photolithography steps. The initial process parameters were carefully varied and adjusted to meet the target specifications (such as threshold voltage, breakdown voltage, gate oxide thickness, etc.) using ATHENA and ATLAS simulation software. After the device fabrication was completed, DC testing was performed on the fabricated VDMOS transistors both at RIT and at Spectrum Devices. A successful extraction of the transfer curves, family of curves, and breakdown voltage plots both in low and high current settings was achieved. The designed process produced a power VDMOS with a breakdown voltage of up to 180 V, a threshold voltage of ~3.8 V, a transconductance up to ~7 mhos, and an operating current of nearly 5 A. The experimental results were compared to the target specification provided by Spectrum Devices. In addition, impacts of the Faraday shield implant on the breakdown voltage and terminal capacitances of a VDMOS device were verified through DC testing. Preliminary wafer- level AC testing was performed and demonstrated the functional performance of the device up to 100 kHz frequency range. Although it would be interesting to see the impact of UIS implant step on a device performance, no AC test was yet to be performed. This work presented the first power VDMOS transistors successfully fabricated and characterized at RIT. With the data and information obtained from this thesis project, process modifications and adjustments should yield devices with improved performance

An Initial study on The Reliability of Power Semiconductor Devices

An initial literature study combined with some basic comparative simulations has been performed on different electricfield modulation techniques and the subsequent reliability issues are reported for power semiconductor devices. An explanation of the most important power device metrics such as the offstate breakdown (BV) and specific on-resistance (RON) will be given, followed by a short overview of some of the electrostatic techniques (fieldplates, RESURF e.g. [1]) used to suppress peak electric fields. Furthermore it will be addressed that the high current operation of these devices results in shifting electric field peaks (Kirk effect [2], [3]) and as such different avalanche behavior, resulting in (gate oxide) reliability issues unlike those of conventional CMOS

Komponente na bazi silicijum karbida u elektronskim kolima velike snage

Silicon has been the number one choice of materials for over 40 years. It has reached an almost perfected stage through extensive research for so many years; now it is cheap to be manufactured and performs very reliably at room temperature. However, as modem electronics move to a more advanced level with increasing complexity, materials other than silicon are under consideration. Several areas where Silicon shows shortcomings in high temperature environments and high voltage conditions. The Silicon devices need to be shielded – cooled, are limited to operation at low temperature and low blocking voltage by virtue physical and electric properties. So silicon devices are restricted and have focused on low power electronics applications only, these various limitations in the use of Si devices has led to development of wide band gap semiconductors such as Silicon carbide . And because there is an urgent need for high voltage electronics for advanced technology represented in (transportation - space - communications - power systems) in which silicon has failed to be used. Due to various properties of Silicon carbide like lower intrinsic carrier concentration (10–35 orders of magnitude), higher electric breakdown field (4–20 times), higher thermal conductivity (3–13 times), larger saturated electron drift velocity (2–2.5 times),wide band gap (2.2 eV) and higher, more isotropic bulk electron mobility comparable to that of Si. These properties make it a potential material to overcome the limitations of Si. The fact that wide band gap semiconductors are capable of electronic functionality, particularly in the case of SiC. 4H-SiC is a potentially useful material for high temperature devices because of its refractory nature. So Silicon Carbide (SiC) will bring solid-state power electronics to a new horizon by expanding to applications in the high voltage power electronics sectors. It is the better choice for use in high temperature environment and high voltage conditions. Silicon carbide is about to replace Si material very quickly and scientifically will force Si to get retired. The superior characteristics of silicon carbide, have suggested considering as the next generation of power semiconductor devices. And because our study will concentrate on the use of semiconductors on high voltage unipolar power electronics devices. DIMOSFET will be..

Large signal design of silicon field effect transistors for linear radio frequency power amplifiers

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SiC/Al4SiC4-Based Heterostructure Transistors

A wide-band-gap (WBG) SiC/Al4SiC4 heterostructure transistor with a gate length of 5 μm is designed using a ternary carbide of Al4SiC4, and its performance is simulated by Silvaco Atlas. The simulations use a mixture of parameters obtained from ensemble Monte Carlo simulations, DFT calculations, and experimental data. The 5 μm gate length transistor is then laterally scaled to 2 and 1 μm gate length devices. The 5 μm gate length SiC/Al4SiC4 heterostructure transistor delivers a maximum drain current of 168 mA/mm, which increases to 244 mA/mm and 350 mA/mm for gate lengths of 2 and 1 μm, respectively. The device breakdown voltage is 59.0 V, which reduces to 31.0 V and to 18.0 V in the scaled 2 μm and the 1 μm gate length transistors, respectively. The scaled down 1 μm gate length device switches faster thanks to a higher transconductance of 65.1 mS/mm compared to only 1.69 mS/mm for the 5 μm gate length device. Finally, the subthreshold slope of the scaled devices is 197.3, 97.6, and 96.1 mV/dec for gate lengths of 5, 2, and 1 μm, respectively

Novel 3-D IC technology

textFor many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).Electrical and Computer Engineerin

Radiation Effects on Semiconductor Devices in High Energy Heavy Ion Accelerators

Radiation effects on semiconductor devices in GSI Helmholtz Center for Heavy Ion Research are becoming more and more significant with the increase of beam intensity due to upgrades. Moreover a new accelerator is being constructed on the basis of GSI within the project of facility for antiproton and ion research (FAIR). Beam intensities will be increased by factor of 100 and energies by factor of 10. Radiation fields in the vicinity of beam lines will increase more than 2 orders of magnitude and so will the effects on semiconductor devices. It is necessary to carry out a study of radiation effects on semiconductor devices considering specific properties of radiation typical for high energy heavy ion accelerators. Radiation effects on electronics in accelerator environment may be divided into two categories: short-term temporary effects and long-term permanent degradation. Both may become critical for proper operation of some electronic devices. This study is focused on radiation damage to CCD cameras in radiation environment of heavy ion accelerator. Series of experiments with irradiation of devices under test (DUTs) by secondary particles produced during ion beam losses were done for this study. Monte Carlo calculations were performed to simulate the experiment conditions and conditions expected in future accelerator. Corresponding comparisons and conclusions were done. Another device typical for accelerator facilities - industrial Ethernet switch was tested in similar conditions during this study. Series of direct irradiations of CCD and MOS transistors with heavy ion beams were done as well. Typical energies of the primary ion beams were 0.5-1 GeV/u. Ion species: from Na to U. Intensities of the beam up to 1e9 ions/spill with spill length of 200-300 ns. Criteria of reliability and lifetime of DUTs in specific radiation conditions were formulated, basing on experimental results of the study. Predictions of electronic device reliability and lifetime were formulated for radiation conditions expected in future at FAIR, basing on Monte Carlo simulations. In addition to main results a new type of CCD-based beam loss monitor (BLM) was proposed and discussed

Prikaz stanja silicijevih MOS upravljanih učinskih sklopova i PiN ispravljača

Revolutionary advances and developments have been made in power semiconductor device technologies during the last decades which have allowed the improvement of power electronic systems in terms of their efficiency and reliability. The advent of MOS-gated power switches such as the power MOSFET and the IGBT showing high input impedance has been a real breakthrough in the design and fabrication of power electronic systems. This paper reviews the recent progress in the development of Si MOS-gated power devices and rectifiers. The evolution of these devices’ technologies together with the introduction of revolutionary device concepts is also discussed. Concretely, the introduction of trench technologies for power MOSFETs and the use of the super-junction concept for breaking the 1D-silicon limit are highlighted. Developments in IGBTs such as those based on the use of thin wafers and strategies for optimising the plasma distribution in PT IGBTs during the on-state are also addressed. Finally, advances in PiN diode technologies including new concepts for both the anode and the cathode structures are also reviewed. These approaches have allowed the reduction of the PiN total losses and a soft reverse recovery behaviour, leading to a more rugged device.U posljednjim desetljećima svjedočimo razvoju sustava učinske elektronike u pogledu povećanja efikasnosti i pouzdanosti. Napredak je omogućen zahvaljujući izvanrednom napredku koji je postignut na području učinskih poluvodiča. Pojava MOS upravljanih učinskih sklopova s visokom ulaznom impedancijom, kao što su MOSFET i IGBT, rezultirao je probojem u projektiranju i proizvodnji sustava učinske elekronike. Ovaj članak daje uvid u napredak koji je u posljednje vrijeme ostvaren u razvoju silicijeve MOS upravljane učinske elektronike i ispravljača. Uz dosadašnji razvoj tehnologije navedenih komponenata, u članku je uključen i osvrt na revolucionarne koncepte budućeg razvoja. Konkretno, u radu su objašnjene tehnologija rova za MOSFET i korištenje koncepta super spoja za probijanje granice jednodimenzionalnog silicija. Razmatrana su i poboljšanja IGBT-ova koja se baziraju na uporabi tankih pločica a strategijama optimiranja distribucije plazme u PT IGBT-ovima za vrijeme aktivnog stanja. Konačno, prikazan je i napredak u tehnologiji PiN dioda koji uključuje nove strukturalne koncepte katode i anode. Ovi pristupi su omogućili smanjenje ukupnih gubitaka PiN diode i blagu dinamiku reverznog oporavka, što rezultira povećanjem robusnosti sklopa