SiC/Al4SiC4-Based Heterostructure Transistors

Abstract

A wide-band-gap (WBG) SiC/Al4SiC4 heterostructure transistor with a gate length of 5 μm is designed using a ternary carbide of Al4SiC4, and its performance is simulated by Silvaco Atlas. The simulations use a mixture of parameters obtained from ensemble Monte Carlo simulations, DFT calculations, and experimental data. The 5 μm gate length transistor is then laterally scaled to 2 and 1 μm gate length devices. The 5 μm gate length SiC/Al4SiC4 heterostructure transistor delivers a maximum drain current of 168 mA/mm, which increases to 244 mA/mm and 350 mA/mm for gate lengths of 2 and 1 μm, respectively. The device breakdown voltage is 59.0 V, which reduces to 31.0 V and to 18.0 V in the scaled 2 μm and the 1 μm gate length transistors, respectively. The scaled down 1 μm gate length device switches faster thanks to a higher transconductance of 65.1 mS/mm compared to only 1.69 mS/mm for the 5 μm gate length device. Finally, the subthreshold slope of the scaled devices is 197.3, 97.6, and 96.1 mV/dec for gate lengths of 5, 2, and 1 μm, respectively