An Application of Haar Wavelet Decomposition in Video Frames Preservation in Association with Visual Cryptography

Visual cryptography is one of the techniques used to encode the video by separating the original video. The proposed Visual cryptography gives the show to the users how encryption and decryption can be done to the video. Waveletchange are to provide characteristic of multiple declarationand worldwide decomposition that are the important features for thevideo compression application. The privacy and security becomes the most significant issues since the multimedia is transmitted openly over the network. A new adapted Haar Wavelet is used to encrypt the full video in an capable protected manner, after encryption the frame will decomposes and audio send final uncompressed video

A Benchmarking assessment of known visual cryptography algorithms

With the growth of digital media, it is becoming more prevalent to find a method to protect the security of that media. An effective method for securely transmitting images is found in the field of Visual Cryptography. While this method is effective for securely transmitting images, many methods have been developed since the first algorithm was proposed in 1994 by Naor and Shamir. A benchmarking scheme is proposed to give the algorithm capabilities, understand the implementation method, evaluate the algorithm development, and provide image reconstruction information. Additionally, the algorithms are ranked according to a Visual Cryptography standard. This would allow an easy way to differentiate between algorithms and determine the ideal algorithm for a given task or project

Survey and future trends of efficient cryptographic function implementations on GPGPUs

Many standard cryptographic functions are designed to benefit from hardware specific implementations. As a result, there have been a large number of highly efficient ASIC and FPGA hardware based implementations of standard cryptographic functions. Previously, hardware accelerated devices were only available to a limited set of users. General Purpose Graphic Processing Units (GPGPUs) have become a standard consumer item and have demonstrated orders of magnitude performance improvements for general purpose computation, including cryptographic functions. This paper reviews the current and future trends in GPU technology, and examines its potential impact on current cryptographic practice

Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes

Modern embedded systems have an emerging demand on high performance and low power circuits. Traditionally special functional units for each application are developed separately. These are plugged to a general purpose processors to extend its instruction set making it an application specific instruction set processor. As this strategy reaches its boundaries in area and complexity reconfigurable architectures propose to be more flexible. Thus combining both approaches to a reconfigurable application specific processor is going to be the upcoming solution for future embedded systems

Private and Public-Key Side-Channel Threats Against Hardware Accelerated Cryptosystems

Modern side-channel attacks (SCA) have the ability to reveal sensitive data from non-protected hardware implementations of cryptographic accelerators whether they be private or public-key systems. These protocols include but are not limited to symmetric, private-key encryption using AES-128, 192, 256, or public-key cryptosystems using elliptic curve cryptography (ECC). Traditionally, scalar point (SP) operations are compelled to be high-speed at any cost to reduce point multiplication latency. The majority of high-speed architectures of contemporary elliptic curve protocols rely on non-secure SP algorithms. This thesis delivers a novel design, analysis, and successful results from a custom differential power analysis attack on AES-128. The resulting SCA can break any 16-byte master key the sophisticated cipher uses and it\u27s direct applications towards public-key cryptosystems will become clear. Further, the architecture of a SCA resistant scalar point algorithm accompanied by an implementation of an optimized serial multiplier will be constructed. The optimized hardware design of the multiplier is highly modular and can use either NIST approved 233 & 283-bit Kobliz curves utilizing a polynomial basis. The proposed architecture will be implemented on Kintex-7 FPGA to later be integrated with the ARM Cortex-A9 processor on the Zynq-7000 AP SoC (XC7Z045) for seamless data transfer and analysis of the vulnerabilities SCAs can exploit

Visual cryptography scheme with digital watermarking in sharing secret information from car number plate digital images

In this paper a visual cryptography scheme with a binary additive stream cipher is used to form the meaningless shares (share images or multiple layers) of original digital image, hiding some secret information. Each share image holds some information, but at the receiver side only when all of them are superimposed, the secret information is revealed by human vision without any complex computation. Proposed algorithm for generating shares is applied in MATLAB programming environment, using MATLAB built-in functions to create sequences of pseudorandom numbers or streams, which are used to make share images of original digital image. The input image is first converted into a binary image, shares are generated using pixel expansion scheme, and after that are sent to the receiver. At the received side, the shares could be printed in separate transparent sheets and overlapped in order to reveal the secret image, with some loss in contrast when compared to the original image. An algorithm is applied to car number plate digital images with watermark. Digital image watermarking method is used to embed some data in a car number plate digital image in order to verify the credibility of the content or the identity of the owner

Formal Verification of Receipt Validation in Chaum’s Scheme

In the aftermath of the United States Presidential election, more and more frequently there are calls for voters to be able to place their votes from the comfort of their own home. However, many studies have found prototype systems to be either insecure or insufficiently defined for the purposes of an election on a national scale. In this paper I will examine the security of voting applications from a different angle: the validation and verification of compiled code. There are the obvious concerns about unverified code, that we have no guarantee the protocol described by the voting procedure is the one being executed. Using work by Appel [3] as a model, it can be seen that even advanced cryptographic algorithms can be verified. Using Chaum’s scheme, a visual cryptography system intensely examined in Staub’s work [1], and originally described in Chaum’s paper [5], as our target enables us to have a secure algorithm that we can properly verify. Our goal will be to establish a verified code implementation for Chaum’s scheme that could be deployed to voters to confirm their votes

High-performance AES-128 algorithm implementation by FPGA-based SoC for 5G communications

none4siIn this research work, a fast and lightweight AES-128 cypher based on the Xilinx ZCU102 FPGA board is presented, suitable for 5G communications. In particular, both encryption and decryption algorithms have been developed using a pipelined approach, so enabling the simultaneous processing of the rounds on multiple data packets at each clock cycle. Both the encryption and decryption systems support an operative frequency up to 220 MHz, reaching 28.16 Gbit/s maximum data throughput; besides, the encryption and decryption phases last both only ten clock periods. To guarantee the interoperability of the developed encryption/decryption system with the other sections of the 5G communication apparatus, synchronization and control signals have been integrated. The encryption system uses only 1631 CLBs, whereas the decryption one only 3464 CLBs, ascribable, mainly, to the Inverse Mix Columns step. The developed cypher shows higher efficiency (8.63 Mbps/slice) than similar solutions present in literature.openP.Visconti, R. Velazquez, S. Capoccia, R. de FazioVisconti, P.; Velazquez, R.; Capoccia, S.; de Fazio, R