719 research outputs found
An Experimental Microarchitecture for a Superconducting Quantum Processor
Quantum computers promise to solve certain problems that are intractable for
classical computers, such as factoring large numbers and simulating quantum
systems. To date, research in quantum computer engineering has focused
primarily at opposite ends of the required system stack: devising high-level
programming languages and compilers to describe and optimize quantum
algorithms, and building reliable low-level quantum hardware. Relatively little
attention has been given to using the compiler output to fully control the
operations on experimental quantum processors. Bridging this gap, we propose
and build a prototype of a flexible control microarchitecture supporting
quantum-classical mixed code for a superconducting quantum processor. The
microarchitecture is based on three core elements: (i) a codeword-based event
control scheme, (ii) queue-based precise event timing control, and (iii) a
flexible multilevel instruction decoding mechanism for control. We design a set
of quantum microinstructions that allows flexible control of quantum operations
with precise timing. We demonstrate the microarchitecture and microinstruction
set by performing a standard gate-characterization experiment on a transmon
qubit.Comment: 13 pages including reference. 9 figure
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Automatic Generation of Cognitive Theories using Genetic Programming
Cognitive neuroscience is the branch of neuroscience that studies the neural mechanisms underpinning cognition and develops theories explaining them. Within cognitive neuroscience, computational neuroscience focuses on modeling behavior, using theories expressed as computer programs. Up to now, computational theories have been formulated by neuroscientists. In this paper, we present a new approach to theory development in neuroscience: the automatic generation and testing of cognitive theories using genetic programming. Our approach evolves from experimental data cognitive theories that explain âthe mental programâ that subjects use to solve a specific task. As an example, we have focused on a typical neuroscience experiment, the delayed-match-to-sample (DMTS) task. The main goal of our approach is to develop a tool that neuroscientists can use to develop better cognitive theories
The architecture of a video image processor for the space station
The architecture of a video image processor for space station applications is described. The architecture was derived from a study of the requirements of algorithms that are necessary to produce the desired functionality of many of these applications. Architectural options were selected based on a simulation of the execution of these algorithms on various architectural organizations. A great deal of emphasis was placed on the ability of the system to evolve and grow over the lifetime of the space station. The result is a hierarchical parallel architecture that is characterized by high level language programmability, modularity, extensibility and can meet the required performance goals
Virtual memory
Virtual memory was conceived as a way to automate overlaying of program segments. Modern computers have very large main memories, but need automatic solutions to the relocation and protection problems. Virtual memory serves this need as well and is thus useful in computers of all sizes. The history of the idea is traced, showing how it has become a widespread, little noticed feature of computers today
First steps towards the certification of an ARM simulator using Compcert
The simulation of Systems-on-Chip (SoC) is nowadays a hot topic because,
beyond providing many debugging facilities, it allows the development of
dedicated software before the hardware is available. Low-consumption CPUs such
as ARM play a central role in SoC. However, the effectiveness of simulation
depends on the faithfulness of the simulator. To this effect, we propose here
to prove significant parts of such a simulator, SimSoC. Basically, on one hand,
we develop a Coq formal model of the ARM architecture while on the other hand,
we consider a version of the simulator including components written in
Compcert-C. Then we prove that the simulation of ARM operations, according to
Compcert-C formal semantics, conforms to the expected formal model of ARM. Size
issues are partly dealt with using automatic generation of significant parts of
the Coq model and of SimSoC from the official textual definition of ARM.
However, this is still a long-term project. We report here the current stage of
our efforts and discuss in particular the use of Compcert-C in this framework.Comment: First International Conference on Certified Programs and Proofs 7086
(2011
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