Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Investigation of Cu‑Cu bonding for 2.5D and 3D system integration using self‑assembled monolayer as oxidation inhibitor

Das Cu-Cu-Bonden ist eine vielversprechende lötfreie Fine-Pitch-Verbindungstechnologie für die 2,5D- und 3D-Systemintegration. Diese Bondtechnologie wurde in den letzten Jahren intensiv untersucht und wird derzeit für miniaturisierte mikroelektronische Produkte eingesetzt. Allerdings, stellt das Cu‑Cu-Bonden zum einen sehr hohe Anforderungen an die Oberflächenplanarität und -reinheit, und zum anderen sollten die Bondpartner frei von Oxiden sein. Oxidiertes Cu erfordert erhöhte Bondparameter, um die Oxidschicht zu durchbrechen und zuverlässige Cu-Cu-Verbindungen zu erzielen. Diese Bondbedingungen sind für viele sensible Bauelemente nicht geeignet. Aus diesem Grund sollten alternative Technologien mit einer einfachen Technik zum Schutz von Cu vor Oxidation gefunden werden. In dieser Arbeit werden selbstorganisierte Monolagen (SAMs) für den Cu-Oxidationsschutz und die Verbesserung der Cu-Cu-Thermokompression- (TC) und Ultraschall- (US) Flip-Chip-Bondtechnologien untersucht. Die Experimente werden an Si-Chips mit galvanisch aufgebrachten Cu-Microbumps und Cu-Schichten durchgeführt. Die Arbeit beinhaltet die umfassende Charakterisierung der SAM für den Cu-Schutz, die Bewertung der technologischen Parameter für das TC- und US-Flip-Chip-Bonden sowie die Charakterisierung der Cu-Cu-Bondqualität (Scherfestigkeitstests, Bruchflächen- und Mikrostrukturanalysen). Eine Lagerung bei tiefen Temperaturen (bei ‑18 °C und ‑40 °C) bestätigte die langanhaltende Schutzwirkung der kurzkettigen SAMs für das galvanisch abgeschiedene Cu ohne chemisch-mechanische Politur. Der Einfluss der Tieftemperaturlagerung an Luft und der thermischen SAM-Desorption in einer Inertgasatmosphäre auf die TC-Verbindungsqualität wird im Detail analysiert. Die Idee, mit Hilfe der US-Leistung SAM mechanisch zu entfernen und gleichzeitig das US-Flip-Chip-Bonden zu starten, wurde in der Literatur bisher nicht systematisch untersucht. Die Methode ermöglicht kurze Bondzeiten, niedrige Bondtemperaturen und das Bonden an Umgebungsluft. Sowohl beim TC- als auch beim US-Flip-Chip-Bonden zeigt es sich, dass die Scherfestigkeit bei den Proben mit SAM-Passivierung um ca. 30 % höher ist als bei unbeschichteten Proben. Das Vorhandensein von Si- und Ti-Bruchflächen nach den Scherfestigkeitstests ist für die Proben mit der SAM-Passivierung typisch, was auf eine höhere Festigkeit solcher Verbindungen im Vergleich zu ungeschützten Proben schließen lässt. Die Transmissionselektronenmikroskopie (TEM) zeigt keine SAM-Spuren im zentralen Bereich der Cu-Cu-Grenzfläche nach dem US-Flip-Chip-Bonden. Die Ergebnisse dieser Arbeit zeigen die Verbesserung der Bondqualität durch den Einsatz von SAM zum Schutz des Cu vor Oxidation im Vergleich zum üblicherweise angewandten Cu-Vorätzen. Das gefundene technologische Prozessfenster für das US-Flip-Chip-Bonden an Luft bietet eine hohe Bondqualität bei 90 °C und 150 °C, bei 180 MPa, bei einer Bonddauer von 1 s an. Die in dieser Arbeit gewonnenen Erkenntnisse sind ein wichtiger Beitrag zum Verständnis des SAM-Einflusses auf Chips mit galvanischen Cu-Microbumps, bzw. Cu-Schichten, und zur weiteren Anwendung der Cu-Cu-Fine-Pitch-Bondtechnologie in der Mikroelektronik.Cu-Cu bonding is one of the most promising fine-pitch interconnect technologies with solder elimination for 2.5D and 3D system integration. This bonding technology has been intensively investigated in the last years and is currently in application for miniaturized microelectronics products. However, Cu-Cu bonding has very high demands on the sur-face planarity and purity, and the bonding partners should be oxide-free. Oxidized Cu requires elevated bonding parameters in order to break through the oxide layer and achieve reliable Cu-Cu interconnects. Those bonding conditions are undesirable for many devices (e.g. due to the temperature/pressure sensitivity). Therefore, alternative technologies with a simple technique for Cu protection from oxidation are required. Self-assembled monolayers (SAMs) are proposed for the Cu protection and the improvement of the Cu-Cu thermocompression (TC) and ultrasonic (US) flip-chip bonding technologies in this thesis. The experiments were carried out on Si dies with electroplated Cu microbumps and Cu layers. The thesis comprises the comprehensive characterization of the SAM for Cu protection, evaluation of technological parameters for TC and US flip-chip bonding as well as characterization of the Cu-Cu bonding quality (shear strength tests, fracture surface and microstructure analyses). The storage at low temperatures (at ‑18 °C and ‑40 °C) confirmed the prolonged protective effect of the short-chain SAMs for the electroplated Cu without chemical-mechanical polishing. The influence of the low-temperature storage in air and the thermal SAM desorption in an inert gas atmosphere on the TC bonding quality was analyzed in detail. The approach of using US power to mechanically remove SAM and simultaneously start the US flip-chip bonding has not been systematically investigated before. The method provides the benefit of short bonding time, low bonding temperature and bonding in ambient air. Both the TC and US flip-chip bonding results featured the shear strength that is approximately 30 % higher for the samples with SAM passivation in comparison to the uncoated samples. The presence of Si and Ti fracture surfaces after the shear strength tests is typical for the samples with the SAM passivation, which suggests a higher strength of such interconnects in comparison to the uncoated samples. The transmission electron microscopy (TEM) indicated no SAM traces at the central region of the Cu-Cu bonding interface after the US flip-chip bonding. The results of this thesis show the improvement of the bonding quality caused by the application of SAM for Cu protection from oxidation in comparison to the commonly applied Cu pre-treatments. The found technological process window for the US flip-chip bonding in air offers high bonding quality at 90 °C and 150 °C, at 180 MPa, for the bonding duration of 1 s. The knowledge gained in this thesis is an important contribution to the understanding of the SAM performance on chips with electroplated Cu microbumps/layers and further application of the Cu-Cu fine-pitch bonding technology for microelectronic devices

Novel fine pitch interconnection methods using metallised polymer spheres

There is an ongoing demand for electronics devices with more functionality while reducing size and cost, for example smart phones and tablet personal computers. This requirement has led to significantly higher integrated circuit input/output densities and therefore the need for off-chip interconnection pitch reduction. Flip-chip processes utilising anisotropic conductive adhesives anisotropic conductive films (ACAs/ACFs) have been successfully applied in liquid crystal display (LCD) interconnection for more than two decades. However the conflict between the need for a high particle density, to ensure sufficient the conductivity, without increasing the probability of short circuits has remained an issue since the initial utilization of ACAs/ACFs for interconnection. But this issue has become even more severe with the challenge of ultra-fine pitch interconnection. This thesis advances a potential solution to this challenge where the conductive particles typically used in ACAs are selectively deposited onto the connections ensuring conductivity without bridging. The research presented in this thesis work has been undertaken to advance the fundamental understanding of the mechanical characteristics of micro-sized metal coated polymer particles (MCPs) and their application in fine or ultra-fine pitch interconnections. This included use of a new technique based on an in-situ nanomechanical system within SEM which was utilised to study MCP fracture and failure when undergoing deformation. Different loading conditions were applied to both uncoated polymer particles and MCPs, and the in-situ system enables their observation throughout compression. The results showed that both the polymer particles and MCP display viscoelastic characteristics with clear strain-rate hardening behaviour, and that the rate of compression therefore influences the initiation of cracks and their propagation direction. Selective particle deposition using electrophoretic deposition (EPD) and magnetic deposition (MD) of Ni/Au-MCPs have been evaluated and a fine or ultra-fine pitch deposition has been demonstrated, followed by a subsequent assembly process. The MCPs were successfully positively charged using metal cations and this charging mechanism was analysed. A new theory has been proposed to explain the assembly mechanism of EPD of Ni/Au coated particles using this metal cation based charging method. The magnetic deposition experiments showed that sufficient magnetostatic interaction force between the magnetized particles and pads enables a highly selective dense deposition of particles. Successful bonding to form conductive interconnections with pre-deposited particles have been demonstrated using a thermocompression flip-chip bonder, which illustrates the applicable capability of EPD of MCPs for fine or ultra-fine pitch interconnection

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis work aims at fabricating through-silicon vias (TSVs) on diced processor chips, and later bonding them into a 3D-stacked chip. How to handle and process delicate processor chips with high alignment precision is a key issue. The TSV process to be developed also needs to adapt to this constraint. Four TSV processes have been studied. Among them, the ring-trench TSV process demonstrates the feasibility of fabricating TSVs with the prevailing dimensions, and the whole-through TSV process achieves the first dummy chip post-processed with TSVs in EPFL although the dimension is rather large to keep a reasonable aspect ratio (AR). Four self-alignment (SA) techniques have been investigated, among which the gravitational SA and the hydrophobic SA are found to be quite promising. Using gravitational SA, we come to the conclusion that cavities in silicon carrier wafer with a profile angle of 60° can align the chips with less than 20 µm inaccuracies. The alignment precision can be improved after adopting more advanced dicing tools instead of using the traditional dicing saws and larger cavity profile angle. Such inaccuracy will be sufficient to align the relatively large TSVs for general products such as 3D image sensors. By fabricating bottom TSVs in the carrier wafer, a 3D silicon interposer idea has been proposed to stack another chip, e.g. a processor chip, on the other side of the carrier wafer. But stacking microprocessor chips fabricated with TSVs will require higher alignment precision. A hydrophobic SA technique using the surface tension force generated by the water-to-air interfaces around the pads can greatly reduce the alignment inaccuracy to less than 1 µm. This low-cost and high throughput SA procedure is processed in air, fully-compatible with current fabrication technologies, and highly stable and repeatable. We present a theoretical meniscus model to predict SA results and to provide the design rules. This technique is quite promising for advanced 3D applications involving logic and heterogeneous stacking. As TSVs' dimensions in the chip-level 3D integration are constrained by the chip-level processes, such as bonding, the smallest TSVs might still be about 5 µm. Thus, the area occupied by the TSVs cannot be neglected. Fortunately, TSVs can withstand very high bandwidths, meaning that data can be serialized and transmitted using less numbers of TSVs. With 20 µm TSVs, the 2-Gb/s 8:1 serial link implemented saves 75% of the area of its 8-bit parallel counterpart. The quasi-serial link proposed can effectively balance the inter-layer bandwidth and the serial links' area consumption. The area model of the serial or quasi-serial links working under higher frequencies provides some guidelines to choose the proper serial link design, and it also predicts that when TSV diameter shrinks to 5 µm, it will be difficult to keep this area benefit if without some novel circuit design techniques. As the serial links can be implemented with less area, the bandwidth per unit area is increased. Two scenarios are studied, single-port memory access and multi-port memory access. The expanded inter-layer bandwidth by serialization does not improve the system performance because of the bus-bottleneck problem. In the latter scenario, the inter-layer ultra-wide bandwidth can be exploited as each memory bank can be accessed randomly through the NoC. Thus further widening the inter-layer bandwidth through serialization, the system performance will be improved

異種ダイレット積層を用いたフレキシブルハイブリッドデバイスの集積技術に関する研究

Tohoku University福島誉史課

Radio Frequency Micro/Nano-Fluidic Devices for Microwave Dielectric Property Characterizations

In this dissertation, a number of different topics in microwave dielectric property measurements have been covered by a systematic approach to the goals of development of dielectric spectroscopy and study of its high electric field effects with integrated on-chip microwave microfluidic / nanofluidic devices. A method of parasitic effects cancellation for dielectric property measurement is proposed, analyzed, and experimentally evaluated for microwave characterization of small devices and materials that yield low intensity signals. The method dramatically reduces parasitic effects to uncover the otherwise buried signals. A high-sensitive radio frequency (RF) device is then developed and fabricated to detect small dielectric property changes in microfluidic channel. Sensitivity improvement via on-chip transmission line loss compensation is then analyzed and experimentally demonstrated. Different samples are measured and high sensitivity is achieved compared to conventional transmission-line-based methods. High DC electric field effects on dielectric properties of water are investigated with microwave microfluidic devices. Gold microstrip-line-based devices and highly-doped silicon microstrip-line-based devices are exploited. Initiation process of water breakdown in a small gap is discussed. Electrode surface roughness is examined and its effect on observed water breakdown is investigated. It is believed that electrode surface roughness is one of critical factors for the initiation process of water breakdown in small gap system. Finally, water dielectric property subjected to uniform DC electric field in 260 nm planar microfluidic channels is experimentally studied via silicon microstrip-line-based devices. When applied DC field is as high as up to ~ 1 MV/cm, the water is sustained and no breakdown is occurred. Strong water dielectric saturation effects are observed from measured water dielectric spectroscopy. An on-chip, broadband microwave dielectric spectrometer with integrated transmission line and nanofluidic channels is designed, fabricated and characterized through microwave S-parameter measurements. Heavily-doped Si material is used to build the microstrip line to provide broadband characterization capability. 10 nm deep planar Si nanofluidic channels are fabricated through native oxide etch and wafer bonding process. It is the first effort to build the microstrip line with periodically loaded individual sub-10 nm nanofluidic channels to conduct the broadband high frequency characterization of materials within confined space. The functionality of the device is demonstrated by the measurement of DI water. It behaves well and has great potentials on the study of confinement effects of fluids and molecules. Further work includes development of parasitic signal de-embedding procedures for accurate measurements

Microdroplet Technology Based Functional Microcapsules Generation, Handling and Applications

制度:新 ; 報告番号:甲3593号 ; 学位の種類:博士(工学) ; 授与年月日:2012/2/25 ; 早大学位記番号:新593

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined