Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Soft-Error Resilience Framework For Reliable and Energy-Efficient CMOS Logic and Spintronic Memory Architectures

The revolution in chip manufacturing processes spanning five decades has proliferated high performance and energy-efficient nano-electronic devices across all aspects of daily life. In recent years, CMOS technology scaling has realized billions of transistors within large-scale VLSI chips to elevate performance. However, these advancements have also continually augmented the impact of Single-Event Transient (SET) and Single-Event Upset (SEU) occurrences which precipitate a range of Soft-Error (SE) dependability issues. Consequently, soft-error mitigation techniques have become essential to improve systems\u27 reliability. Herein, first, we proposed optimized soft-error resilience designs to improve robustness of sub-micron computing systems. The proposed approaches were developed to deliver energy-efficiency and tolerate double/multiple errors simultaneously while incurring acceptable speed performance degradation compared to the prior work. Secondly, the impact of Process Variation (PV) at the Near-Threshold Voltage (NTV) region on redundancy-based SE-mitigation approaches for High-Performance Computing (HPC) systems was investigated to highlight the approach that can realize favorable attributes, such as reduced critical datapath delay variation and low speed degradation. Finally, recently, spin-based devices have been widely used to design Non-Volatile (NV) elements such as NV latches and flip-flops, which can be leveraged in normally-off computing architectures for Internet-of-Things (IoT) and energy-harvesting-powered applications. Thus, in the last portion of this dissertation, we design and evaluate for soft-error resilience NV-latching circuits that can achieve intriguing features, such as low energy consumption, high computing performance, and superior soft errors tolerance, i.e., concurrently able to tolerate Multiple Node Upset (MNU), to potentially become a mainstream solution for the aerospace and avionic nanoelectronics. Together, these objectives cooperate to increase energy-efficiency and soft errors mitigation resiliency of larger-scale emerging NV latching circuits within iso-energy constraints. In summary, addressing these reliability concerns is paramount to successful deployment of future reliable and energy-efficient CMOS logic and spintronic memory architectures with deeply-scaled devices operating at low-voltages

Optimising image quality for medical imaging

OPTIMAX 2016 was held at the University of Salford in Greater Manchester. It is the fourth summer school of OPTIMAX with other renditions having been organized at the University of Salford (2013), ESTeSL, Lisbon (2014) and Hanze UAS, Groningen (2015). For OPTIMAX 2016, 72 people participated from eleven countries, comprising PhD, MSc and BSc students as well as tutors from the seven European partner universities. Professional mix was drawn from engineering, medical physics/ physics and radiography. OPTIMAX 2016 was partly funded by the partner universities and partly by the participants. Two students from South Africa and two from Brazil were invited by Hanze UAS (Groningen) and ESTeSL (Lisbon). One student from the United Kingdom was funded by the Nuffield Foundation. The summer school included lectures and group projects in which experimental research was conducted in five teams. Each team project focus varied and included: optimization of full spine curvature radiography in paediatrics; ultrasound assessment of muscle thickness and muscle cross-sectional area: a reliability study; the Influence of Source-to-Image Distance on Effective Dose and Image Quality for Mobile Chest X-rays; Impact of the anode heel effect on image quality and effective dose for AP Pelvis: A pilot study; and the impact of pitch values on Image Quality and radiation dose in an abdominal adult phantom using CT. OPTIMAX 2016 culminated in a poster session and a conference, in which the research teams presented their posters and oral presentations. This book comprises of two sections, the first four chapters concern generic background information which has value to summer school organization and also theory on which the research projects were built. The second section contains the research papers in written format. The research papers have been accepted for the ECR conference, Vienna, 2017 as either oral presentations or posters

Optimax 2016 : peer observation of facilitation

In August 2016, a 3-week research Summer School was delivered at University of Salford. The Summer School, known as ‘OPTIMAX’ was in its fourth year of delivery. Previous iterations were held in the Netherlands (2015), Portugal (2014) and Salford (2013). The purpose of OPTIMAX is to facilitate collaborative international and interdisciplinary research between university academics and students. This offers an exceptional opportunity not only for students, but also for tutors who want to develop their facilitation skills. The project reported here used tutor observers (i.e. tutors who attend the summer school, in an observational capacity only, to develop their own skills as teachers) to observe, identify and reflect on a range of facilitation practices for managing the diverse OPTIMAX research groups. The project presents a description of the peer-observation method we used and highlights a number of findings related to facilitator strategies that appeared to influence group dynamics and learning. These observations are then used to make recommendations about how OPTIMAX tutors can be prepared for their facilitation experience

A New Low-Cost Device Based on Thermal Infrared Sensors for Olive Tree Canopy Temperature Measurement andWater Status Monitoring

In recent years, many olive orchards, which are a major crop in the Mediterranean basin, have been converted into intensive or super high-density hedgerow systems. This configuration is more e cient in terms of yield per hectare, but at the same time the water requirements are higher than in traditional grove arrangements. Moreover, irrigation regulations have a high environmental (through water use optimization) impact and influence on crop quality and yield. The mapping of (spatio-temporal) variability with conventional water stress assessment methods is impractical due to time and labor constraints, which often involve staff training. To address this problem, this work presents the development of a new low-cost device based on a thermal infrared (IR) sensor for the measurement of olive tree canopy temperature and monitoring of water status. The performance of the developed device was compared to a commercial thermal camera. Furthermore, the proposed device was evaluated in a commercially managed olive orchard, where two different irrigation treatments were established: a full irrigation treatment (FI) and a regulated deficit irrigation (RDC), aimed at covering 100% and 50% of crop evapotranspiration (ETc), respectively. Predawn leaf water potential (YPD) and stomatal conductance (gs), two widely accepted indicators for crop water status, were regressed to the measured canopy temperature. The results were promising, reaching a coeffcient of determination R2 > 0.80. On the other hand, the crop water stress index (CWSI) was also calculated, resulting in a coeffcient of determination R2 > 0.79. The outcomes provided by the developed device support its suitability for fast, low-cost, and reliable estimation of an olive orchard’s water status, even suppressing the need for supervised acquisition of reference temperatures. The newly developed device can be used for water management, reducing water usage, and for overall improvements to olive orchard management.The research and APC were funded by the Interreg Cooperation Program V-A SPAIN-PORTUGAL (POCTEP) 2014–2020 and co-financed with ERDF (European Regional Development Fund), grant number 0155_TECNOLIVO_6_E, within the scope of the TecnOlivo Project. Dr. Borja Millán is funded by the Spanish Ministry of Science, Innovation, and Universities through a Juan de la Cierva-Formación Grant (FJCI-2017-31824).The research and APC were funded by the Interreg Cooperation Program V-A SPAIN-PORTUGAL (POCTEP) 2014–2020 and co-financed with ERDF (European Regional Development Fund), grant number 0155_TECNOLIVO_6_E, within the scope of the TecnOlivo Project. Dr. Borja Mill á n is funded by the Spanish Ministry of Science, Innovation, and Universities through a Juan de la Cierva-Formaci ó n Grant (FJCI-2017-31824)

Thermal & electrical simulation for the development of solid-phase polycrystalline silicon TFTs

Solid phase crystallization (SPC) is a processing technique used for conversion of amorphous silicon (a-Si) to polycrystalline silicon (poly-Si). SPC can potentially be used as an alternative to excimer laser annealing to fabricate the semiconductor layer for thin-film transistors (TFTs) in active-matrix liquid crystal display (AMLCD). It is a technique suitable for large-area applications since it involves easily scalable thermal processes in the form of rapid thermal annealing (RTA) and furnace annealing (FA). The SPC parameter space involves the time and temperature of the FA, and the time, temperature, and number of pulses in the RTA process. In developing new process flows for thin-film transistors (TFTs) using SPC, thermal and electrical device simulation are invaluable tools. Comsol® was utilized to explore this SPC experimental parameter space, and provided important insight on temperature conditions not directly measureable on glass substrates (see Fig. 1). Silvaco\u27s Atlas® was utilized to evaluate the TFT response variables of sub-threshold slope (SS), threshold voltage (VT), and maximum current (Imax). Further, a procedure for fitting TFT device characteristics using Atlas was developed. From this simulation fit (see Fig. 2), theoretical trap state distributions for the semiconducting film can be extracted, as well as the trap state distributions at the oxide-semiconductor interfaces

Self-healing concepts involving fine-grained redundancy for electronic systems

The start of the digital revolution came through the metal-oxide-semiconductor field-effect transistor (MOSFET) in 1959 followed by massive integration onto a silicon die by means of constant down scaling of individual components. Digital systems for certain applications require fault-tolerance against faults caused by temporary or permanent influence. The most widely used technique is triple module redundancy (TMR) in conjunction with a majority voter, which is regarded as a passive fault mitigation strategy. Design by functional resilience has been applied to circuit structures for increased fault-tolerance and towards self-diagnostic triggered self-healing. The focus of this thesis is therefore to develop new design strategies for fault detection and mitigation within transistor, gate and cell design levels. The research described in this thesis makes three contributions. The first contribution is based on adding fine-grained transistor level redundancy to logic gates in order to accomplish stuck-at fault-tolerance. The objective is to realise maximum fault-masking for a logic gate with minimal added redundant transistors. In the case of non-maskable stuck-at faults, the gate structure generates an intrinsic indication signal that is suitable for autonomous self-healing functions. As a result, logic circuitry utilising this design is now able to differentiate between gate faults and faults occurring in inter-gate connections. This distinction between fault-types can then be used for triggering selective self-healing responses. The second contribution is a logic matrix element which applies the three core redundancy concepts of spatial- temporal- and data-redundancy. This logic structure is composed of quad-modular redundant structures and is capable of selective fault-masking and localisation depending of fault-type at the cell level, which is referred to as a spatiotemporal quadded logic cell (QLC) structure. This QLC structure has the capability of cellular self-healing. Through the combination of fault-tolerant and masking logic features the QLC is designed with a fault-behaviour that is equal to existing quadded logic designs using only 33.3% of the equivalent transistor resources. The inherent self-diagnosing feature of QLC is capable of identifying individual faulty cells and can trigger self-healing features. The final contribution is focused on the conversion of finite state machines (FSM) into memory to achieve better state transition timing, minimal memory utilisation and fault protection compared to common FSM designs. A novel implementation based on content-addressable type memory (CAM) is used to achieve this. The FSM is further enhanced by creating the design out of logic gates of the first contribution by achieving stuck-at fault resilience. Applying cross-data parity checking, the FSM becomes equipped with single bit fault detection and correction

Communications systems technology assessment study. Volume 2: Results

The cost and technology characteristics are examined for providing special satellite services at UHF, 2.5 GHz, and 14/12 GHz. Considered are primarily health, educational, informational and emergency disaster type services. The total cost of each configuration including space segment, earth station, installation operation and maintenance was optimized to reduce the user's total annual cost and establish preferred equipment performance parameters. Technology expected to be available between now and 1985 is identified and comparisons made between selected alternatives. A key element of the study is a survey of earth station equipment updating past work in the field, providing new insight into technology, and evaluating production and test methods that can reduce costs in large production runs. Various satellite configurations were examined. The cost impact of rain attenuation at Ku-band was evaluated. The factors affecting the ultimate capacity achievable with the available orbital arc and available bandwidth were analyzed