High-density interconnect technology assessment of printed circuit boards for space applications

High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs

I/O port macromodelling

3D electromagnetic modelling and simulation of various Printed Circuit Board (PCB) components is an important technique for characterizing the Signal Integrity (SI) and Electromagnetic Compatibility (EMC) issues present in a PCB. However, due to limited computational resource and the complexity of the integrated circuits, it is currently not possible to fully model a complete PCB system with 3D electromagnetic solvers. An effort has been made to fully model the PCB with all its components and their S-parameters has been derived so as to integrate these S-parameters in 1D, 2D static or quasi-static field solver or circuit solver tool. The novelty of this thesis is the development and verification of active circuit such as Input and Output buffers and passive channel components such as interconnects, via and connectors and deriving their S-parameters in order to model and characterize the complete PCB using 3D full field solver based on Transmission Line Matrix modelling (TLM) method. An integration of Input/Output (I/O) port in the 3D full field modelling method allows for modelling of the complete PCB system without being computationally expensive. This thesis presents a method for integration of Input/Output port in the 3D time domain modelling environment. Several software tools are available in the market which can characterize these PCBs in the frequency as well as the time domain using 1D, 2D techniques or using circuit solver such as spice. The work in this thesis looks at extending these 1D and 2D techniques for 3D Electromagnetic solvers in the time domain using the TLM technique for PCB analysis. The modelling technique presented in this thesis is based on in-house developed 3D TLM method along with a developed behavioral Integrated Circuit (IC) – macromodel. The method has been applied to a wide variety of PCB topologies along with a range of IC packages to fully validate the approach. The method has also been applied to show the switching effect arising out of the crosstalk in a logic device apart from modelling various discontinuities of PCB interconnects in the form of S11 and S21 parameters. The proposed novel TLM based technique has been selected based on simplification of its approach, electrical equivalence (rather than complex mathematical functions of Maxwell's electromagnetic theory), time domain analysis for transients in a PCB with an increased accuracy over other available methods in the literature. On the experimental side two, four and six layered PCBs with various interconnect discontinuities such as straight line, right angle, fan-out and via and IC packages such as SOT-23 (DBV), SC-70 (DCK) and SOT-553 (DRL) has been designed and manufactured. The modelling results have been verified with the experimental results of these PCBs and other commercial software such as HSPICE, CST design studio available in the market. While characterizing the SI issues, these modelling results can also help in analyzing conducted and radiated EMC/EMI problems to meet various EMC regulations such as CE, FCC around the world

I/O port macromodelling

3D electromagnetic modelling and simulation of various Printed Circuit Board (PCB) components is an important technique for characterizing the Signal Integrity (SI) and Electromagnetic Compatibility (EMC) issues present in a PCB. However, due to limited computational resource and the complexity of the integrated circuits, it is currently not possible to fully model a complete PCB system with 3D electromagnetic solvers. An effort has been made to fully model the PCB with all its components and their S-parameters has been derived so as to integrate these S-parameters in 1D, 2D static or quasi-static field solver or circuit solver tool. The novelty of this thesis is the development and verification of active circuit such as Input and Output buffers and passive channel components such as interconnects, via and connectors and deriving their S-parameters in order to model and characterize the complete PCB using 3D full field solver based on Transmission Line Matrix modelling (TLM) method. An integration of Input/Output (I/O) port in the 3D full field modelling method allows for modelling of the complete PCB system without being computationally expensive. This thesis presents a method for integration of Input/Output port in the 3D time domain modelling environment. Several software tools are available in the market which can characterize these PCBs in the frequency as well as the time domain using 1D, 2D techniques or using circuit solver such as spice. The work in this thesis looks at extending these 1D and 2D techniques for 3D Electromagnetic solvers in the time domain using the TLM technique for PCB analysis. The modelling technique presented in this thesis is based on in-house developed 3D TLM method along with a developed behavioral Integrated Circuit (IC) – macromodel. The method has been applied to a wide variety of PCB topologies along with a range of IC packages to fully validate the approach. The method has also been applied to show the switching effect arising out of the crosstalk in a logic device apart from modelling various discontinuities of PCB interconnects in the form of S11 and S21 parameters. The proposed novel TLM based technique has been selected based on simplification of its approach, electrical equivalence (rather than complex mathematical functions of Maxwell's electromagnetic theory), time domain analysis for transients in a PCB with an increased accuracy over other available methods in the literature. On the experimental side two, four and six layered PCBs with various interconnect discontinuities such as straight line, right angle, fan-out and via and IC packages such as SOT-23 (DBV), SC-70 (DCK) and SOT-553 (DRL) has been designed and manufactured. The modelling results have been verified with the experimental results of these PCBs and other commercial software such as HSPICE, CST design studio available in the market. While characterizing the SI issues, these modelling results can also help in analyzing conducted and radiated EMC/EMI problems to meet various EMC regulations such as CE, FCC around the world

XNAP: A Novel Two-Dimensional X-Ray Detector for Time Resolved Synchrotron Applications

The XNAP project develops a demonstration system for a spatially resolving detector with timing capabilities in the nanosecond range. A dense array of avalanche photodiodes is combined with multiple readout ASICs to build the detector hybrid. On an area of nearly 1 cm2, single photons can be counted within each of the 1k pixels. After 20 years of continuous improvements during operation, the ESRF Synchrotron is going to be upgraded substantially by the replacement of major parts of the source and the beamlines. For experimental techniques that will benefit from the increased brilliance, research into X-ray detectors is required. The requirements for the novel detector are composed of the distinguished properties of multiple state-of-the-art detector systems, shifted towards technical limits. The specification is transferred into the design of the sensor, ASIC, interposing structure and the readout system. A smaller prototype detector is built to resolve implementation challenges ahead of its large-scale accomplishment. Emphasis is put on the ASIC, and parallel approaches for the interconnecting technology and the readout system are carried out. The usability of the smaller prototype system is demonstrated with measurements of microfocus X-ray and Synchrotron light. Parts of the final detector are characterized at the laboratory prior to its commissioning

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

FAST: a scintillating tracker for antiproton cross section measurements

A scintillating fiber tracker (FAST, Fiber Antiproton Scintillating Tracker) has been developed in the framework of the ASACUSA collaboration to perform a low energy antiproton cross section measurement at the Antiproton Decelerator at CERN; this PhD Thesis will discuss the design, the development, the commissioning of the FAST detector and the preliminary results of the data taking held in July 2007. Chap. 1 is a review of the topical results in Antiproton Physics during the last 50 years. Chap. 2 focuses on detectors; since the detector chosen for our experiment is a scintillating fiber tracker, the most advanced fiber detection systems are reviewed. Chap. 3 describes the detector, a 2500 channel scintillating fiber tracker readout by 42 multianode photomultipliers a custom electronics. The design has been validated with montecarlo simulations and with dedicated beam tests on prototypes. The tracker has been tested with cosmic rays to characterize the efficiency, the time resolution and the spatial resolution. Chap. 4 describes the commissioning phase and reports the results of the data collected on the Antiproton Decelerator. In the last Chap. 3 applications of the system developed for FAST in different physics fields are shown. The electronics has been used in Medical Physics, allowing a ToF neutron detection in a radiotherapic environment, in imaging applications, connected to a GEM pad detector and as a beam profile monitor with high rate capabilities at the CERN SPS H8 beam line

Commissioning Perspectives for the ATLAS Pixel Detector

The ATLAS Pixel Detector, the innermost sub-detector of the ATLAS experiment at the Large Hadron Collider, CERN, is an 80 million channel silicon pixel tracking detector designed for high-precision charged particle tracking and secondary vertex reconstruction. It was installed in the ATLAS experiment and commissioning for the first proton-proton collision data taking in 2008 has begun. Due to the complex layout and limited accessibility, quality assurance measurements were continuously performed during production and assembly to ensure that no problematic components are integrated. The assembly of the detector at CERN and related quality assurance measurement results, including comparison to previous production measurements, will be presented. In order to verify that the integrated detector, its data acquisition readout chain, the ancillary services and cooling system as well as the detector control and data acquisition software perform together as expected approximately 8% of the detector system was progressively assembled as close to the final layout as possible. The so-called System Test laboratory setup was operated for several months under experiment-like environment conditions. The interplay between different detector components was studied with a focus on the performance and tunability of the optical data transmission system. Operation and optical tuning procedures were developed and qualified for the upcoming commission ing. The front-end electronics preamplifier threshold tuning and noise performance were studied and noise occupancy of the detector with low sensor bias voltages was investigated. Data taking with cosmic muons was performed to test the data acquisition and trigger system as well as the offline reconstruction and analysis software. The data quality was verified with an extended version of the pixel online monitoring package which was implemented for the ATLAS Combined Testbeam. The detector raw data of the Combined Testbeam and of the System Test cosmic run was converted for offline data analysis with the Pixel bytestream converter which was continuously extended and adapted according to the offline analysis software needs

Digitally driven microfabrication of 3D multilayer embedded electronic systems

The integration of multiple digitally driven processes is seen as the solution to many of the current limitations arising from standalone Additive Manufacturing (AM) techniques. A technique has been developed to digitally fabricate fully functioning electronics using a unique combination of AM technologies. This has been achieved by interleaving bottom-up Stereolithography (SL) with Direct Writing (DW) of conductor materials alongside mid-process development (optimising the substrate surface quality), dispensing of interconnects, component placement and thermal curing stages. The resulting process enables the low-temperature production of bespoke three-dimensional, fully packaged and assembled multi-layer embedded electronic circuitry. Two different Digital Light Processing (DLP) Stereolithography systems were developed applying different projection orientations to fabricate electronic substrates by selective photopolymerisation. The bottom up projection orientation produced higher quality more planar surfaces and demonstrated both a theoretical and practical feature resolution of 110 μm. A top down projection method was also developed however a uniform exposure of UV light and planar substrate surface of high quality could not be achieved. The most advantageous combination of three post processing techniques to optimise the substrate surface quality for subsequent conductor deposition was determined and defined as a mid-processing procedure. These techniques included ultrasonic agitation in solvent, thermal baking and additional ultraviolet exposure. SEM and surface analysis showed that a sequence including ultrasonic agitation in D-Limonene with additional UV exposure was optimal. DW of a silver conductive epoxy was used to print conductors on the photopolymer surface using a Musashi dispensing system that applies a pneumatic pressure to a loaded syringe mounted on a 3-axis print head and is controlled through CAD generated machine code. The dispensing behaviour of two isotropic conductive adhesives was characterised through three different nozzle sizes for the production of conductor traces as small as 170 μm wide and 40 μm high. Additionally, the high resolution dispensing of a viscous isotropic conductive adhesive (ICA) also led to a novel deposition approach for producing three dimensional, z-axis connections in the form of high freestanding pillars with an aspect ratio of 3.68 (height of 2mm and diameter of 550μm). Three conductive adhesive curing regimes were applied to printed samples to determine the effect of curing temperature and time on the resulting material resistivity. A temperature of 80 °C for 3 hours resulted in the lowest resistivity while displaying no substrate degradation. ii Compatibility with surface mount technology enabled components including resistors, capacitors and chip packages to be placed directly onto the silver adhesive contact pads before low-temperature thermal curing and embedding within additional layers of photopolymer. Packaging of components as small as 0603 surface mount devices (SMDs) was demonstrated via this process. After embedding of the circuitry in a thick layer of photopolymer using the bottom up Stereolithography apparatus, analysis of the adhesive strength at the boundary between the base substrate and embedding layer was conducted showing that loads up to 1500 N could be applied perpendicular to the embedding plane. A high degree of planarization was also found during evaluation of the embedding stage that resulted in an excellent surface finish on which to deposit subsequent layers. This complete procedure could be repeated numerous times to fabricate multilayer electronic devices. This hybrid process was also adapted to conduct flip-chip packaging of bare die with 195 μm wide bond pads. The SL/DW process combination was used to create conductive trenches in the substrate surface that were filled with isotropic conductive adhesive (ICA) to create conductive pathways. Additional experimentation with the dispensing parameters led to consistent 150 μm ICA bumps at a 457 μm pitch. A flip-chip bonding force of 0.08 N resulted in a contact resistance of 2.3 Ω at a standoff height of ~80 μm. Flip-chips with greater standoff heights of 160 μm were also successfully underfilled with liquid photopolymer using the SL embedding technique, while the same process on chips with 80 μm standoff height was unsuccessful. Finally the approaches were combined to fabricate single, double and triple layer circuit demonstrators; pyramid shaped electronic packages with internal multilayer electronics; fully packaged and underfilled flip-chip bare die and; a microfluidic device facilitating UV catalysis. This new paradigm in manufacturing supports rapid iterative product development and mass customisation of electronics for a specific application and, allows the generation of more dimensionally complex products with increased functionality

CMOS-Based Peptide Arrays

CMOS - Based Peptide Arrays Peptide arrays are an important tool in proteomics and peptidomics, allowing a large number of peptides to be synthesized on a common support and exposed to a solution of target molecules in parallel. In particle-based synthesis, the amino acids for in situ synthesis of peptides are transported to synthesis loci in solid particles and released upon melting, allowing an increase in density over liquid-based systems. This thesis focuses on the development of application-specific high voltage integrated circuits for electrostatic deposition of charged amino acid particles and their integration into a combinatorial peptide synthesis system. Transfer of amino acid particles from the aerosol to synthesis loci on the chip surface was investigated for a pixel pitch between 45 µm and 100 µm, and compatibility between the chips, particle transfer and the poly(ethylene glycol)methacrylate - based surface modifi¬cations was established. The first combinatorial syntheses on CMOS chips were performed with over 16,000 distinct synthesis sites per chip, at a density of 10,000 spots per cm2, which is a 25-fold increase over the 400 spots per cm2 currently available on laser-printed glass slides. For FLAG and HA peptide epitopes, immonostaining showed regular spots of comparable signal intensity over the whole chip area