Performance of an Echo Canceller and Channel Estimator for On-Channel Repeaters in DVB-T/H Networks

This paper investigates the design and performance of an FIR echo canceller for on-channel repeaters in DVB-T/H network within the framework of the PLUTO project. The possible approaches for echo cancellation are briefly reviewed and the main guidelines for the design of such systems are presented. The main system parameters are discussed. The performance of an FIR echo canceller based on an open loop feedforward approach for channel estimation is tested for different radio channel conditions and for different number of taps of the FIR filter. It is shown that a minimum number of taps is recommended to achieve a certain mean rejection ratio or isolation depending on the type of channel. The expected degradation in performance due to the use of fixed point rather than floating point arithmetic in hardware implementation is presented for different number of bits. Channel estimation based on training sequences is investigated. The performance of Maximum Length Sequences and Constant Amplitude Zero Autocorrelation (CAZAC) Sequences is compared for different channels. Recommendations are given for training sequence type, length and level for DVB-T/H on-channel repeater deployment

INVESTIGATIVE STUDY OF VOICE AND DATA COMMUNICATION OVER POWER LINE COMMUNICATION SYSTEM

Communication is the transfer of information from one point to another over a channel. However, as technology is growing, more information is needed to be passed over large distances for the realization of the world being a global village. There is the need to place a reliable communication system that will transmit effortlessly both data and voice over a channel. Power Line Communication (PLC) also known as Broadband over Power Line (BPL) technology offers high speed and broadband communication services to homes connected to the power lines. This makes use of the electrical lines for transmission of data up to the last mile and there is no need of separating copper cables, short haul satellite systems, optical fibre cable and Wi-Fi. This work presented an overview of a voice and data communication over PLC in terms of the various types, equipment use, method of communication, application, regulatory activities on PLC and the challenges facing the implementation of power line for transmitting voice and data. Therefore, PLC is a viable alternative to all other methods of transmission as it is readily available and can be easily implemented in rural areas where other communication systems are not implemented for the transmission of voice and data communication. Keywords: Communication, Power Line Communication, Broadband over Power Line, Voice and Data Communication, Broadband over Power Line, Transmission, Electrical Line. DOI: 10.7176/MTM/9-8-03 Publication date: August 31st 201

Application of advanced on-board processing concepts to future satellite communications systems: Bibliography

Abstracts are presented of a literature survey of reports concerning the application of signal processing concepts. Approximately 300 references are included

Deliverable D4.1: VLC modulation schemes

This report presents the analysis of different modulation schemes D4.1 for VLC systems of the VIDAS project. Considering the final prototype design and application, the deliverable D4.1 was projected. The detail analysis of various modulation schemes are carried out and a robust technique based on direct sequence spread spectrum (DSSS) is followed. DSSS technique though necessitates use of high bandwidth while minimizing the effect of noise. Since the final application does not require very high dat a rate of transmission but robustness against the noise (external lights) becomes necessary. The analysis is followed by model development using Matlab/Simulink. The performance of both of these systems are compared and evaluated. Some of the simulation results are presented

Antimultipath communication by injecting tone into null in signal spectrum

A transmitter for digital radio communication creates a null by balanced encoding of data modulated on an RF carrier, and inserts a calibration tone within the null. This is accomplished by having the calibration tone coincide in phase and frequency with the transmitted radio frequency output, for coherent demodulation of data at the receiver where the tone calibration signal is extracted and used for multipath fading compensation

Simulation of DSL systems

-This report contains simulations of performance for different versions of ADSL, VDSL and SHDSL in 0.4 mm twisted pair cables. An important part of the work has been to investigate the compatibility between different DSL systems. The range of SHDSL system compliant with ITU G.991.2 Annex G has been analysed. These systems allow for bitrates up to 3.848 Mbit/s and 5.696 Mbit/ for 16-PAM and 32-PAM systems respectively. The overall conclusion is that downstream ADSL and ADSL2+ is compatible with both SHDSL Annex G and HDSL systems. The degradation in bitrate of downstream ADSL due to these systems is moderate, less than 13% compared to a cable containing only ADSL systems. ADSL subloop means that an ADSL DSLAM is installed between the local exchange and the subscriber. The purpose is to reduce the loop length between the DSLAM and the subscriber in order to increase the bitrate. This subloop signal will represent a strong interference in the downstream direction of the ADSL systems from the local exchange. As is shown in Section 7 in this report there is a severe degradation in the downstream direction of the ADSL system from the local exchange. The remedy to reduce this degradation is to use power backoff in the subloop systems. Use of power backoff regimes is not analysed in this report. The potential bitrates for VDSL2 systems have been analysed for bandplans 997 and 998. The simulations show that bandplan 997 will give almost symmetrical up- and downstream bitrates for the cables less than 800 meters, whereas for bandplan 998 the downstream/upstream ratio is close to 2:1. Three different bandwidths have been analysed, 12 MHz, 17 MHz and 30 MHz. The frequency bands above 12 MHz are used only for loop lengths less than 800 meters. The frequency bands above 17 MHz are used only for loop lengths less than 650 meters. Bandplans that makes use of the lowest upstream band U0 can still provide adequate upstream capacity (1 Mbit/s) even for loop lengths in excess of 2 km. The downstream bitrate is significant (17-18 Mbit/s) for both 997 and 998 at these lengths. A discussion of the use of ADSL in equalisation cables is given in Section 9. Alternative ways to install ADSL in pairs that contain 1+1 systems are presented in Section 10. Oppdragsgiver: Post- og teletilsyne

Low-swing signaling for energy efficient on-chip networks

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 65-69).On-chip networks have emerged as a scalable and high-bandwidth communication fabric in many-core processor chips. However, the energy consumption of these networks is becoming comparable to that of computation cores, making further scaling of core counts difficult. This thesis makes several contributions to low-swing signaling circuit design for the energy efficient on-chip networks in two separate projects: on-chip networks optimized for one-to-many multicasts and broadcasts, and link designs that allow on-chip networks to approach an ideal interconnection fabric. A low-swing crossbar switch, which is based on tri-state Reduced-Swing Drivers (RSDs), is presented for the first project. Measurement results of its test chip fabricated in 45nm SOI CMOS show that the tri-state RSD-based crossbar enables 55% power savings as compared to an equivalent full-swing crossbar and link. Also, the measurement results show that the proposed crossbar allows the broadcast-optimized on-chip networks using a single pipeline stage for physical data transmission to operate at 21% higher data rate, when compared with the full-swing networks. For the second project, two clockless low-swing repeaters, a Self-Resetting Logic Repeater (SRLR) and a Voltage-Locked Repeater (VLR), have been proposed and analyzed in simulation only. They both require no reference clock, differential signaling, and bias current. Such digital-intensive properties enable them to approach energy and delay performance of a point-to-point interconnect of variable lengths. Simulated in 45nm SOI CMOS, the 10mm SRLR featured with high energy efficiency consumes 338fJ/b at 5.4Gb/s/ch while the 10mm VLR raises its data rate up to 16.OGb/s/ch with 427fJ/b.by Sunghyun Park.S.M