Design of energy efficient high speed I/O interfaces

Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input

Silicon-Organic Hybrid (SOH) Mach-Zehnder Modulators for 100 Gbit/s On-Off Keying

Electro-optic modulators for high-speed on-off keying (OOK) are key components of short- and mediumreach interconnects in data-center networks. Besides small footprint and cost-efficient large-scale production, small drive voltages and ultra-low power consumption are of paramount importance for such devices. Here we demonstrate that the concept of silicon-organic hybrid (SOH) integration is perfectly suited for meeting these challenges. The approach combines the unique processing advantages of large-scale silicon photonics with unrivalled electro-optic (EO) coefficients obtained by molecular engineering of organic materials. In our proof-of-concept experiments, we demonstrate generation and transmission of OOK signals with line rates of up to 100 Gbit/s using a 1.1 mm-long SOH Mach-Zehnder modulator (MZM) which features a {\pi}-voltage of only 0.9 V. This experiment represents not only the first demonstration of 100 Gbit/s OOK on the silicon photonic platform, but also leads to the lowest drive voltage and energy consumption ever demonstrated at this data rate for a semiconductor-based device. We support our experimental results by a theoretical analysis and show that the nonlinear transfer characteristic of the MZM can be exploited to overcome bandwidth limitations of the modulator and of the electric driver circuitry. The devices are fabricated in a commercial silicon photonics line and can hence be combined with the full portfolio of standard silicon photonic devices. We expect that high-speed power-efficient SOH modulators may have transformative impact on short-reach optical networks, enabling compact transceivers with unprecedented energy efficiency that will be at the heart of future Ethernet interfaces at Tbit/s data rates

Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies

Low Cost, Robust, Environmentally Friendly Geopolymer–Mesoporous Carbon Composites for Efficient Solar Powered Steam Generation

High-efficiency, environment friendly, renewable energy-based methods of desalination represent attractive and potentially very powerful solutions to the long-standing problem of global water shortage. Many new laboratory-scale materials have been developed for photothermal desalination but the development of low-cost, easy-to-manufacture, and scalable materials and systems that can convert solar irradiation into exploitable thermal energy in this context is still a significant challenge. This paper presents work on a geopolymer–biomass mesoporous carbon composite (GBMCC) device with mesoporous and macroporous structures for harvesting solar energy, which is then used in a device to generate water vapor with high efficiency using negative pressure, wind-driven, steam generation. The GBMCC device gives water evaporation rates of 1.58 and 2.71 kg m−2 h−1 under 1 and 3 suns illumination, with the solar thermal conversion efficiency up to 84.95% and 67.6%, respectively. A remarkable, record high water vapor generation rate of 7.55 kg m−2 h−1 is achieved under 1 sun solar intensity at the wind speed of 3 m s−1. This is a key step forward todays efficient, sustainable and economical production of clean water from seawater or common wastewater with free solar energy

Tuning domain wall velocity with Dzyaloshinskii-Moriya interaction

We have studied a series of Pt/Co/M epitaxial trilayers, in which Co is sandwiched between Pt and a non magnetic layer M (Pt, Ir, Cu, Al). Using polar magneto-optical Kerr microscopy, we show that the field- induced domain wall speeds are strongly dependent on the nature of the top layer, they increase going from M=Pt to lighter top metallic overlayers, and can reach several 100 m/s for Pt/Co/Al. The DW dynamics is consistent with the presence of chiral N\'eel walls stabilized by interfacial Dzyaloshinskii-Moriya interaction (DMI) whose strength increases going from Pt to Al top layers. This is explained by the presence of DMI with opposite sign at the Pt/Co and Co/M interfaces, the latter increasing in strength going towards heavier atoms, possibly due to the increasing spin-orbit interaction. This work shows that in non-centrosymmetric trilayers the domain wall dynamics can be finely tuned by engineering the DMI strength, in view of efficient devices for logic and spitronics applications.Comment: 5 pages, 4 Figure

The Design of a System Architecture for Mobile Multimedia Computers

This chapter discusses the system architecture of a portable computer, called Mobile Digital Companion, which provides support for handling multimedia applications energy efficiently. Because battery life is limited and battery weight is an important factor for the size and the weight of the Mobile Digital Companion, energy management plays a crucial role in the architecture. As the Companion must remain usable in a variety of environments, it has to be flexible and adaptable to various operating conditions. The Mobile Digital Companion has an unconventional architecture that saves energy by using system decomposition at different levels of the architecture and exploits locality of reference with dedicated, optimised modules. The approach is based on dedicated functionality and the extensive use of energy reduction techniques at all levels of system design. The system has an architecture with a general-purpose processor accompanied by a set of heterogeneous autonomous programmable modules, each providing an energy efficient implementation of dedicated tasks. A reconfigurable internal communication network switch exploits locality of reference and eliminates wasteful data copies