Power efficient simple technique to convert a reset-and-hold into a true-sample-and-hold using an auxiliary output stage

A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation by only 1.3%. The circuit is offset-compensated and has close to rail-to-rail swing. Experimental results of a test chip prototype in 130nm CMOS technology with 0.3mW power dissipation are provided, which validate the proposed technique.This work was supported by a Grant TEC2016-80396-C2 (AEI/FEDER). The work of Héctor Daniel Rico-Aniles was supported by the Mexican Consejo Nacional de Ciencia y Tecnología (CONACYT) through an academic scholarship under Grant 408946

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation

Infrared imaging technology, used both to study deep-space bodies' radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm 2 chip integrated in a standard 0.18-μm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping, analog calibration, nor digital compensation technique. When coupled to a IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW

Rail-to-Rail Operational in Low-Power Reconfigurable Analog Circuitry

Analog signal processing (ASP) can be used to decrease energy consumption by several orders of magnitude over completely digital applications. Low-power field programmable analog arrays (FPAA) have been previously used by analog designers to decrease energy consumption. Combining ASP with an FPAA, energy consumption of these systems can be further reduced. For ASP to be most functional, it must achieve rail-to-rail operation to maintain a high dynamic range. This work strives to further reduce power consumption in reconfigurable analog circuitry by presenting a novel data converter that utilizes ASP and rail-to-rail operation. Rail-to-Rail operation is achieved in the data converter with the use of an operational amplifier presented in this work. This efficient yet elementary data converter has been fabricated in a 0.5$\mu$m standard CMOS process. Additionally, this work looks deeper into the challenges of students working remotely, how MATLAB can be used to create circuit design tools, and how these developmental tools can be used by circuit design students

An Ultra Low Power Digital to Analog Converter Optimized for Small Format LCD Applications

Liquid crystal displays (LCDs) for mobile applications present a unique design challenge. These small format displays can be found primarily in cell phones and PDAs which are devices that have particularly stringent power requirements. At the same time, the displays are increasing in resolution with every generation. This is creating demand for new LCD display technologies. The predominant amorphous thin film transistor technology is no longer feasible in the new high resolution small format screens due to the fact that the displays require too many connections to the driver and the aperture ratios do not allow high density displays. New technologies such as low temperature polysilicon (LTPS) displays continue to shrink in size and increase in resolution. LTPS technology enables the display manufacturer to create relatively high quality transistors on the glass. This allows for a display architecture which integrates the gate driver on the glass. Newer LTPS LCDs also enable a high level of multiplexing the sources lines on the glass which allows for a much simpler connection to the display driver chip. The electronic drivers for these display applications must adhere to strict power and area budgets. This work describes a low-power, area efficient, scalable, digital-to-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. The display driver is based on a twelve channel, 9-bit DAC driver. This architecture, suitable for % VGA resolution displays, exhibited a 2 MSPS conversion rate, less than 300 pW power dissipation per channel using a 5 V supply, and a die area of 0.042 mm per DAC. A new performance standard is set for DAC display drivers in joules per bit areal density

Energy Efficiency in Communications and Networks

The topic of "Energy Efficiency in Communications and Networks" attracts growing attention due to economical and environmental reasons. The amount of power consumed by information and communication technologies (ICT) is rapidly increasing, as well as the energy bill of service providers. According to a number of studies, ICT alone is responsible for a percentage which varies from 2% to 10% of the world power consumption. Thus, driving rising cost and sustainability concerns about the energy footprint of the IT infrastructure. Energy-efficiency is an aspect that until recently was only considered for battery driven devices. Today we see energy-efficiency becoming a pervasive issue that will need to be considered in all technology areas from device technology to systems management. This book is seeking to provide a compilation of novel research contributions on hardware design, architectures, protocols and algorithms that will improve the energy efficiency of communication devices and networks and lead to a more energy proportional technology infrastructure

Improved Accuracy Area Efficient Hybrid CMOS/GaN DC-DC Buck Converterfor High Step-Down Ratio Applications

abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.Dissertation/ThesisMasters Thesis Electrical Engineering 201

CMOS analog-digital circuit components for low power applications

Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction circuits for energy harvester. The main contribution of this work is the realization of low power consumption and high efficient circuit components employable in a management circuit for piezoelectricbased energy harvester. This thesis focuses on the development of current references and operational amplifiers addressing low power demands. A brief literature review is conducted on the components necessary for the power extraction circuit, including introduction to CMOS technology design and research of known low power circuits. It is presented with multiple implementations for voltage and current references, as well for operational amplifier designs. A self-biased current reference, capable of driving the remaining harvesting circuit, is designed and verified. A novel operational amplifier is proposed by the use of a minimum current selector circuit topology. It is a three-stage amplifier with an AB class output stage, comprised by a translinear circuit. The circuit is designed, taking into consideration noise reduction. The circuit components are designed based on the 0.35mm CMOS technology. A physical layout is developed for fabrication purposes. This technology was chosen with consideration of robustness, costliness and performance. The current reference is capable of outputting a stable 12nA current, which may remain stable in a broad range of power supply voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW, with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração de energia com base num elemento piezoelétrico. Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um amplificador operacional com baixa exigência de consumo. Uma revisão da literatura é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor (CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações de referência de tensão e corrente são consideradas, e amplificadores operacionais também. Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e verificada. Um amplificador operacional original é proposto com uma topologia de seleção de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na sua implementação. Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em conta o seu custo versus desempenho. A referência de corrente produz uma corrente de 12nA, permanecendo estável para tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima mantida no estágio de saída