Power efficient simple technique to convert a reset-and-hold into a true-sample-and-hold using an auxiliary output stage

Abstract

A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation by only 1.3%. The circuit is offset-compensated and has close to rail-to-rail swing. Experimental results of a test chip prototype in 130nm CMOS technology with 0.3mW power dissipation are provided, which validate the proposed technique.This work was supported by a Grant TEC2016-80396-C2 (AEI/FEDER). The work of Héctor Daniel Rico-Aniles was supported by the Mexican Consejo Nacional de Ciencia y Tecnología (CONACYT) through an academic scholarship under Grant 408946