Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Runtime Hardware Reconfiguration in Wireless Sensor Networks for Condition Monitoring

The integration of miniaturized heterogeneous electronic components has enabled the deployment of tiny sensing platforms empowered by wireless connectivity known as wireless sensor networks. Thanks to an optimized duty-cycled activity, the energy consumption of these battery-powered devices can be reduced to a level where several years of operation is possible. However, the processing capability of currently available wireless sensor nodes does not scale well with the observation of phenomena requiring a high sampling resolution. The large amount of data generated by the sensors cannot be handled efficiently by low-power wireless communication protocols without a preliminary filtering of the information relevant for the application. For this purpose, energy-efficient, flexible, fast and accurate processing units are required to extract important features from the sensor data and relieve the operating system from computationally demanding tasks. Reconfigurable hardware is identified as a suitable technology to fulfill these requirements, balancing implementation flexibility with performance and energy-efficiency. While both static and dynamic power consumption of field programmable gate arrays has often been pointed out as prohibitive for very-low-power applications, recent programmable logic chips based on non-volatile memory appear as a potential solution overcoming this constraint. This thesis first verifies this assumption with the help of a modular sensor node built around a field programmable gate array based on Flash technology. Short and autonomous duty-cycled operation combined with hardware acceleration efficiently drop the energy consumption of the device in the considered context. However, Flash-based devices suffer from restrictions such as long configuration times and limited resources, which reduce their suitability for complex processing tasks. A template of a dynamically reconfigurable architecture built around coarse-grained reconfigurable function units is proposed in a second part of this work to overcome these issues. The module is conceived as an overlay of the sensor node FPGA increasing the implementation flexibility and introducing a standardized programming model. Mechanisms for virtual reconfiguration tailored for resource-constrained systems are introduced to minimize the overhead induced by this genericity. The definition of this template architecture leaves room for design space exploration and application- specific customization. Nevertheless, this aspect must be supported by appropriate design tools which facilitate and automate the generation of low-level design files. For this purpose, a software tool is introduced to graphically configure the architecture and operation of the hardware accelerator. A middleware service is further integrated into the wireless sensor network operating system to bridge the gap between the hardware and the design tools, enabling remote reprogramming and scheduling of the hardware functionality at runtime. At last, this hardware and software toolchain is applied to real-world wireless sensor network deployments in the domain of condition monitoring. This category of applications often require the complex analysis of signals in the considered range of sampling frequencies such as vibrations or electrical currents, making the proposed system ideally suited for the implementation. The flexibility of the approach is demonstrated by taking examples with heterogeneous algorithmic specifications. Different data processing tasks executed by the sensor node hardware accelerator are modified at runtime according to application requests

Laboratory Directed Research and Development Program FY 2007 Annual Report

The Oak Ridge National Laboratory (ORNL) Laboratory Directed Research and Development (LDRD) program reports its status to the U.S. Department of Energy (DOE) in March of each year. The program operates under the authority of DOE Order 413.2B, 'Laboratory Directed Research and Development' (April 19, 2006), which establishes DOE's requirements for the program while providing the Laboratory Director broad flexibility for program implementation. LDRD funds are obtained through a charge to all Laboratory programs. This report includes summaries for all ORNL LDRD research activities supported during FY 2007. The associated FY 2007 ORNL LDRD Self-Assessment (ORNL/PPA-2008/2) provides financial data and an internal evaluation of the program's management process. ORNL is a DOE multiprogram science, technology, and energy laboratory with distinctive capabilities in materials science and engineering, neutron science and technology, energy production and end-use technologies, biological and environmental science, and scientific computing. With these capabilities ORNL conducts basic and applied research and development (R&D) to support DOE's overarching mission to advance the national, economic, and energy security of the United States and promote scientific and technological innovation in support of that mission. As a national resource, the Laboratory also applies its capabilities and skills to specific needs of other federal agencies and customers through the DOE Work for Others (WFO) program. Information about the Laboratory and its programs is available on the Internet at http://www.ornl.gov/. LDRD is a relatively small but vital DOE program that allows ORNL, as well as other DOE laboratories, to select a limited number of R&D projects for the purpose of: (1) maintaining the scientific and technical vitality of the Laboratory; (2) enhancing the Laboratory's ability to address future DOE missions; (3) fostering creativity and stimulating exploration of forefront science and technology; (4) serving as a proving ground for new research; and (5) supporting high-risk, potentially high-value R&D. Through LDRD the Laboratory is able to improve its distinctive capabilities and enhance its ability to conduct cutting-edge R&D for its DOE and WFO sponsors. To meet the LDRD objectives and fulfill the particular needs of the Laboratory, ORNL has established a program with two components: the Director's R&D Fund and the Seed Money Fund. As outlined in Table 1, these two funds are complementary. The Director's R&D Fund develops new capabilities in support of the Laboratory initiatives, while the Seed Money Fund is open to all innovative ideas that have the potential for enhancing the Laboratory's core scientific and technical competencies. Provision for multiple routes of access to ORNL LDRD funds maximizes the likelihood that novel ideas with scientific and technological merit will be recognized and supported

Addressing the RRAM Reliability and Radiation Soft-Errors in the Memory Systems

With the continuous and aggressive technology scaling, the design of memory systems becomes very challenging. The desire to have high-capacity, reliable, and energy efficient memory arrays is rising rapidly. However, from the technology side, the increasing leakage power and the restrictions resulting from the manufacturing limitations complicate the design of memory systems. In addition to this, with the new machine learning applications, which require tremendous amount of mathematical operations to be completed in a timely manner, the interest in neuromorphic systems has increased in recent years. Emerging Non- Volatile Memory (NVM) devices have been suggested to be incorporated in the design of memory arrays due to their small size and their ability to reduce leakage power since they can retain their data even in the absence of power supply. Compared to other novel NVM devices, the Resistive Random Access Memory (RRAM) device has many advantages including its low-programming requirements, the large ratio between its high and low resistive states, and its compatibility with the Complementary Metal Oxide Semiconductor (CMOS) fabrication process. RRAM device suffers from other disadvantages including the instability in its switching dynamics and its sensitivity to process variations. Yet, one of the popular issues hindering the deployment of RRAM arrays in products are the RRAM reliability and radiation soft-errors. The RRAM reliability soft-errors result from the diffusion of oxygen vacations out of the conductive channels within the oxide material of the device. On the other hand, the radiation soft-errors are caused by the highly energetic cosmic rays incident on the junction of the MOS device used as a selector for the RRAM cell. Both of those soft-errors cause the unintentional change of the resistive state of the RRAM device. While there is research work in literature to address some of the RRAM disadvantages such as the switching dynamic instability, there is no dedicated work discussing the impact of RRAM soft-errors on the various designs to which the RRAM device is integrated and how the soft-errors can be automatically detected and fixed. In this thesis, we bring the attention to the need of considering the RRAM soft-errors to avoid the degradation in design performance. In addition to this, using previously reported SPICE models, which were experimentally verified, and widely adapted system level simulators and test benches, various solutions are provided to automatically detect and fix the degradation in design performance due to the RRAM soft-errors. The main focus in this work is to propose methodologies which solve or improve the robustness of memory systems to the RRAM soft-errors. These memories are expected to be incorporated in the current and futuristic platforms running the advanced machine learning applications. In more details, the main contributions of this thesis can be summarized as: - Provide in depth analysis of the impact of RRAM soft-errors on the performance of RRAM-based designs. - Provide a new SRAM cell which uses the RRAM device to reduce the SRAM leakage power with minimal impact on its read and write operations. This new SRAM cell can be incorporated in the Graphical Processing Unit (GPU) design used currently in the implementation of the machine learning platforms. - Provide a circuit and system solutions to resolve the reliability and radiation soft-errors in the RRAM arrays. These solution can automatically detect and fix the soft-errors with minimum impact on the delay and energy consumption of the memory array. - A framework is developed to estimate the effect of RRAM soft-errors on the performance of RRAM-based neuromorphic systems. This actually provides, for the first time, a very generic methodology through which the device level RRAM soft-errors are mapped to the overall performance of the neuromorphic systems. Our analysis show that the accuracy of the RRAM-based neuromorphic system can degrade by more than 48% due to RRAM soft-errors. - Two algorithms are provided to automatically detect and restore the degradation in RRAM-based neuromorphic systems due to RRAM soft-errors. The system and circuit level techniques to implement these algorithms are also explained in this work. In conclusion, this work offers initial steps for enabling the usage of RRAM devices in products by tackling one of its most known challenges: RRAM reliability and radiation soft-errors. Despite using experimentally verified SPICE models and widely popular system simulators and test benches, the provided solutions in this thesis need to be verified in the future work through fabrication to study the impact of other RRAM technology shortcomings including: a) the instability in its switching dynamics due to the stochastic nature of oxygen vacancies movement, and b) its sensitivity to process variations

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems

XNAP: A Novel Two-Dimensional X-Ray Detector for Time Resolved Synchrotron Applications

The XNAP project develops a demonstration system for a spatially resolving detector with timing capabilities in the nanosecond range. A dense array of avalanche photodiodes is combined with multiple readout ASICs to build the detector hybrid. On an area of nearly 1 cm2, single photons can be counted within each of the 1k pixels. After 20 years of continuous improvements during operation, the ESRF Synchrotron is going to be upgraded substantially by the replacement of major parts of the source and the beamlines. For experimental techniques that will benefit from the increased brilliance, research into X-ray detectors is required. The requirements for the novel detector are composed of the distinguished properties of multiple state-of-the-art detector systems, shifted towards technical limits. The specification is transferred into the design of the sensor, ASIC, interposing structure and the readout system. A smaller prototype detector is built to resolve implementation challenges ahead of its large-scale accomplishment. Emphasis is put on the ASIC, and parallel approaches for the interconnecting technology and the readout system are carried out. The usability of the smaller prototype system is demonstrated with measurements of microfocus X-ray and Synchrotron light. Parts of the final detector are characterized at the laboratory prior to its commissioning

Marshall Space Flight Center Research and Technology Report 2017

This report features over 60 technology development and scientific research efforts that collectively aim to enable new capabilities in spaceflight, expand the reach of human exploration, and reveal new knowledge about the universe in which we live. These efforts include a wide array of strategic developments: launch propulsion technologies that facilitate more reliable, routine, and cost effective access to space; in-space propulsion developments that provide new solutions to space transportation requirements; autonomous systems designed to increase our utilization of robotics to accomplish critical missions; life support technologies that target our ability to implement closed-loop environmental resource utilization; science instruments that enable terrestrial, solar, planetary and deep space observations and discovery; and manufacturing technologies that will change the way we fabricate everything from rocket engines to in situ generated fuel and consumables

STRAINTRONIC NANOMAGNETIC DEVICES FOR NON-BOOLEAN COMPUTING

Nanomagnetic devices have been projected as an alternative to transistor-based switching devices due to their non-volatility and potentially superior energy-efficiency. The energy efficiency is enhanced by the use of straintronics which involves the application of a voltage to a piezoelectric layer to generate a strain which is ultimately transferred to an elastically coupled magnetostrictive nanomaget, causing magnetization rotation. The low energy dissipation and non-volatility characteristics make straintronic nanomagnets very attractive for both Boolean and non-Boolean computing applications. There was relatively little research on straintronic switching in devices built with real nanomagnets that invariably have defects and imperfections, or their adaptation to non-Boolean computing, both of which have been studied in this work. Detailed studies of the effects of nanomagnet material fabrication defects and surface roughness variation (found in real nanomagnets) on the switching process and ultimately device performance of those switches have been performed theoretically. The results of these studies place the viability of straintronics logic (Boolean) and/or memory in question. With a view to analog computing and signal processing, analog spin wave based device operation has been evaluated in the presence of defects and it was found that defects impact their performance, which can be a major concern for the spin wave based device community. Additionally, the design challenge for low barrier nanomagnet which is the building block of binary stochastic neurons based probabilistic computing device in case of real nanomagnets has also been investigated. This study also cast some doubt on the efficacy of probabilistic computing devices. Fortunately, there are some non-Boolean applications based on the collective action of array of nanomagnets which are very forgiving of material defects. One example is image processing using dipole coupled nanomagnets which is studied here and it showed promising result for noise correction and edge enhancement of corrupted pixels in an image. Moreover, a single magneto tunnel junction based microwave oscillator was proposed for the first time and theoretical simulations showed that it is capable of better performance compared to traditional microwave oscillators. The experimental part of this work dealt with spin wave modes excited by surface acoustic waves, studied with time resolved magneto optic Kerr effect (TR-MOKE). New hybrid spin wave modes were observed for the first time. An experiment was carried out to emulate simulated annealing in a system of dipole coupled magnetostrictive nanomagnets where strain served as the simulated annealing agent. This was a promising outcome and it is the first demonstration of the hardware variant of simulated annealing of a many body system based on magnetostrictive nanomagnets. Finally, a giant spin Hall effect actuated surface acoustic wave antenna was demonstrated experimentally. This is the first observation of photon to phonon conversion using spin-orbit torque and although the observed conversion efficiency was poor (1%), it opened the pathway for a new acoustic radiator. These studies complement past work done in the area of straintronics