Superlattice Nanowire Pattern Transfer (SNAP)

During the past 15 years or so, nanowires (NWs) have emerged as a new and distinct class of materials. Their novel structural and physical properties separate them from wires that can be prepared using the standard methods for manufacturing electronics. NW-based applications that range from traditional electronic devices (logic and memory) to novel biomolecular and chemical sensors, thermoelectric materials, and optoelectronic devices, all have appeared during the past few years. From a fundamental perspective, NWs provide a route toward the investigation of new physics in confined dimensions. Perhaps the most familiar fabrication method is the vapor−liquid−solid (VLS) growth technique, which produces semiconductor nanowires as bulk materials. However, other fabrication methods exist and have their own advantages. In this Account, I review a particular class of NWs produced by an alternative method called superlattice nanowire pattern transfer (SNAP). The SNAP method is distinct from other nanowire preparation methods in several ways. It can produce large NW arrays from virtually any thin-film material, including metals, insulators, and semiconductors. The dimensions of the NWs can be controlled with near-atomic precision, and NW widths and spacings can be as small as a few nanometers. In addition, SNAP is almost fully compatible with more traditional methods for manufacturing electronics. The motivation behind the development of SNAP was to have a general nanofabrication method for preparing electronics-grade circuitry, but one that would operate at macromolecular dimensions and with access to a broad materials set. Thus, electronics applications, including novel demultiplexing architectures; large-scale, ultrahigh-density memory circuits; and complementary symmetry nanowire logic circuits, have served as drivers for developing various aspects of the SNAP method. Some of that work is reviewed here. As the SNAP method has evolved into a robust nanofabrication method, it has become an enabling tool for the investigation of new physics. In particular, the application of SNAP toward understanding heat transport in low-dimensional systems is discussed. This work has led to the surprising discovery that Si NWs can serve as highly efficient thermoelectric materials. Finally, we turn toward the application of SNAP to the investigation of quasi-one-dimensional (quasi-1D) superconducting physics in extremely high aspect ratio Nb NWs

Pathway to the PiezoElectronic Transduction Logic Device

The information age challenges computer technology to process an exponentially increasing computational load on a limited energy budget - a requirement that demands an exponential reduction in energy per operation. In digital logic circuits, the switching energy of present FET devices is intimately connected with the switching voltage, and can no longer be lowered sufficiently, limiting the ability of current technology to address the challenge. Quantum computing offers a leap forward in capability, but a clear advantage requires algorithms presently developed for only a small set of applications. Therefore, a new, general purpose, classical technology based on a different paradigm is needed to meet the ever increasing demand for data processing.Comment: in Nano Letters (2015

p-GaAs nanowire MESFETs with near-thermal limit gating

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio $\sim 10^{5}$, on-resistance ~700 k$\Omega$, contact resistance ~30 k$\Omega$, peak transconductance 1.2 $\mu$S/$\mu$m and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates whilst leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance

Fully rubbery integrated electronics from high effective mobility intrinsically stretchable semiconductors

An intrinsically stretchable rubbery semiconductor with high mobility is critical to the realization of high-performance stretchable electronics and integrated devices for many applications where large mechanical deformation or stretching is involved. Here, we report fully rubbery integrated electronics from a rubbery semiconductor with a high effective mobility, obtained by introducing metallic carbon nanotubes into a rubbery semiconductor composite. This enhancement in effective carrier mobility is enabled by providing fast paths and, therefore, a shortened carrier transport distance. Transistors and their arrays fully based on intrinsically stretchable electronic materials were developed, and they retained electrical performances without substantial loss when subjected to 50% stretching. Fully rubbery integrated electronics and logic gates were developed, and they also functioned reliably upon mechanical stretching. A rubbery active matrix based elastic tactile sensing skin to map physical touch was demonstrated to illustrate one of the applications

Versatile stochastic dot product circuits based on nonvolatile memories for high performance neurocomputing and neurooptimization.

The key operation in stochastic neural networks, which have become the state-of-the-art approach for solving problems in machine learning, information theory, and statistics, is a stochastic dot-product. While there have been many demonstrations of dot-product circuits and, separately, of stochastic neurons, the efficient hardware implementation combining both functionalities is still missing. Here we report compact, fast, energy-efficient, and scalable stochastic dot-product circuits based on either passively integrated metal-oxide memristors or embedded floating-gate memories. The circuit's high performance is due to mixed-signal implementation, while the efficient stochastic operation is achieved by utilizing circuit's noise, intrinsic and/or extrinsic to the memory cell array. The dynamic scaling of weights, enabled by analog memory devices, allows for efficient realization of different annealing approaches to improve functionality. The proposed approach is experimentally verified for two representative applications, namely by implementing neural network for solving a four-node graph-partitioning problem, and a Boltzmann machine with 10-input and 8-hidden neurons

Chalcogenide Glass-on-Graphene Photonics

Two-dimensional (2-D) materials are of tremendous interest to integrated photonics given their singular optical characteristics spanning light emission, modulation, saturable absorption, and nonlinear optics. To harness their optical properties, these atomically thin materials are usually attached onto prefabricated devices via a transfer process. In this paper, we present a new route for 2-D material integration with planar photonics. Central to this approach is the use of chalcogenide glass, a multifunctional material which can be directly deposited and patterned on a wide variety of 2-D materials and can simultaneously function as the light guiding medium, a gate dielectric, and a passivation layer for 2-D materials. Besides claiming improved fabrication yield and throughput compared to the traditional transfer process, our technique also enables unconventional multilayer device geometries optimally designed for enhancing light-matter interactions in the 2-D layers. Capitalizing on this facile integration method, we demonstrate a series of high-performance glass-on-graphene devices including ultra-broadband on-chip polarizers, energy-efficient thermo-optic switches, as well as graphene-based mid-infrared (mid-IR) waveguide-integrated photodetectors and modulators

Charge-based silicon quantum computer architectures using controlled single-ion implantation

We report a nanofabrication, control and measurement scheme for charge-based silicon quantum computing which utilises a new technique of controlled single ion implantation. Each qubit consists of two phosphorus dopant atoms ~50 nm apart, one of which is singly ionized. The lowest two energy states of the remaining electron form the logical states. Surface electrodes control the qubit using voltage pulses and dual single electron transistors operating near the quantum limit provide fast readout with spurious signal rejection. A low energy (keV) ion beam is used to implant the phosphorus atoms in high-purity Si. Single atom control during the implantation is achieved by monitoring on-chip detector electrodes, integrated within the device structure, while positional accuracy is provided by a nanomachined resist mask. We describe a construction process for implanted single atom and atom cluster devices with all components registered to better than 20 nm, together with electrical characterisation of the readout circuitry. We also discuss universal one- and two-qubit gate operations for this architecture, providing a possible path towards quantum computing in silicon.Comment: 9 pages, 5 figure

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors

abstract: Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm[superscript 2] and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate