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research
p-GaAs nanowire MESFETs with near-thermal limit gating
Authors
P. Caroff
J. G. Gluschke
+6Â more
P. Krogstrup
F. Meyer
A. P. Micolich
S. Naureen
J. Nygard
A. R. Ullah
Publication date
24 August 2018
Publisher
'American Chemical Society (ACS)'
Doi
Cite
View
on
arXiv
Abstract
Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio
∼
1
0
5
\sim 10^{5}
∼
1
0
5
, on-resistance ~700 k
Ω
\Omega
Ω
, contact resistance ~30 k
Ω
\Omega
Ω
, peak transconductance 1.2
μ
\mu
μ
S/
μ
\mu
μ
m and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates whilst leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance
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