Electro-thermal Model of a Silicon Carbide Power MOSFET

International audienceThis paper proposes an electro thermal model for power silicon carbide (SiC) MOSFET based on the EKV MOSFET structure. The thermal dissipation is modeled as an RC Network. The model is developed for the SiC MOSFET CMD CREE (V, A) and integrated in the Psim, Saber and Pspice simulation software libraries for prototyping. The simulation curves are compared with the manufacturers' data-sheet

Accurate Time-segmented Loss Model for SiC MOSFETs in Electro-thermal Multi-Rate Simulation

Compared with silicon (Si) power devices, Silicon carbide (SiC) devices have the advantages of fast switching speed and low on-resistance. However, the effects of non-ideal characteristics of SiC MOSFETs and stray parameters (especially parasitic inductance) on switching losses need to be further evaluated. In this paper, a transient loss model based on SiC MOSFET and SiC Schottky barrier diode (SBD) switching pairs is proposed. The transient process analysis is simplified by time segmentation of the transient process of power switching devices. The electro-thermal simulation calculates the junction temperature and updates the temperature-related parameters with the proposed loss model and the thermal network model. A multi-rate data exchange strategy is proposed to solve the problem of disparity in timescales between circuit simulation and thermal network simulation. The CREE CMF20120D SiC MOSFET device is used for the experimental verification. The experimental results verify the accuracy of the model which provides guidance for the circuit design of SiC MOSFETs. All the parameters of the loss model can be extracted from the datasheet, which is practical in power electronics design

Compact electrothermal reliability modeling and experimental characterization of bipolar latchup in SiC and CoolMOS power MOSFETs

In this paper, a compact dynamic and fully coupled electrothermal model for parasitic BJT latchup is presented and validated by measurements. The model can be used to enhance the reliability of the latest generation of commercially available power devices. BJT latchup can be triggered by body-diode reverse-recovery hard commutation with high dV/dt or from avalanche conduction during unclamped inductive switching. In the case of body-diode reverse recovery, the base current that initiates BJT latchup is calculated from the solution of the ambipolar diffusion equation describing the minority carrier distribution in the antiparallel p-i-n body diode. For hard commutation with high dV/dt, the displacement current of the drain-body charging capacitance is critical for BJT latchup, whereas for avalanche conduction, the base current is calculated from impact ionization. The parasitic BJT is implemented in Simulink using the Ebers-Moll model and the temperature is calculated using a thermal network matched to the transient thermal impedance characteristic of the devices. This model has been applied to CoolMOS and SiC MOSFETs. Measurements show that the model correctly predicts BJT latchup during reverse recovery as a function of forward-current density and temperature. The model presented, when calibrated correctly by device manufacturers and applications engineers, is capable of benchmarking the robustness of power MOSFETs

A comprehensive study on the avalanche breakdown robustness of silicon carbide power MOSFETs

This paper presents an in-depth investigation into the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs comprising of functional as well as structural characterization and the corresponding underlying physical mechanisms responsible for device failure. One aspect of robustness for power MOSFETs is determined by its ability to withstand energy during avalanche breakdown. Avalanche energy (EAV) is an important figure of merit for all applications requiring load dumping and/or to benefit from snubber-less converter design. 2D TCAD electro-thermal simulations were performed to get important insight into the failure mechanism of SiC power MOSFETs during avalanche breakdow

Electrical and thermal modeling and aging study of a C2M0025120D silicon carbide-based power MOSFET transistor

International audienceIn most papers studies about MOSFETs aging are treated from a materiel point of view, in this paper we consider the electrical aspects that contribute to such degradation. Two important degradation mechanisms are proposed related to the transistor bias and the increase of its temperature. This study consists to push the studied transistor to operate in an aging mode by imposing particular bias conditions and excessive junction temperature. Based on some electrical quantities, such as drain leakage current and on the junction temperature, the behavior of the transistor is deduced when operating in aging mode. The simulation results obtained show that during these particular operations, the junction temperature increases, which may destroy the transistor

Modelling framework for parallel SiC power MOSFETs chips in modules developed by planar technology

This paper presents a modelling framework to simulate transients and steady state performance for SiC power MOSFETs modules. The electro-thermal modelling is implemented using Simscape/MATLAB program based on the single chip characteristics provided in the datasheet. The method can easily incorporate multiple chips and module parasitic components providing a tool for module characterization and to support module design optimization. The simulated model is then experimentally validated at different voltage buses and junction temperatures for a novel SiC MOSFET Module design consists of two parallel chips per switch developed using wire-bond free planar technology

シリコンカーバイドパワーMOSFETsの破壊耐量ならびにそのメカニズムに関する研究

筑波大学 (University of Tsukuba)201

Global electro-thermal modelling and circuit-type simulation of SiC Mosfet power devices in short-circuit operation for critical system analysis

International audienceThe purpose of this paper is to present, for the first time, a global transient electrothermal model and simulation results of commercially recent silicon carbide (SiC) power MOSFET devices. The developed models aim is faithfully transposing specifically experimental short-circuit (SC) behaviour of the studied components, ready-to-use for the analysis of an inverter-leg malfunctioning. After extensive experimentation, a thermal model of the SiC die allows to develop models of gate-leakage current and drain-source current during SC. After verifying the robustness of the proposed models, an original circuit-type with an easy implementation is performed using a commercial circuit simulation tool

Circuit-type modelling of SiC power Mosfet in short-circuit operation including selective fail-to-open and fail-to-short modes competition

International audienceSiC Mosfet has very unique properties in extreme operation such as a well-known fail-to-short failure mode but in competition with a lesser known fail-to-open failure mode. These two modes are generally studied and modelled separately, whereas, in practice, they are coupled with the junction temperature of the chip. This paper presents a circuit-type modelling approach of these two modes simultaneously. This modelling allows to simulate the selectivity and competition between these two modes, one is clearly critical and the other is advantageously safe. The proposed model is then compared with short-circuit test of 1.2kV-80m MOSFET SiC