Influence of strain on the functionality of ink-jet printed thin films and devices on flexible substrates

Ink-jet printed devices on the flexible substrate are inexpensive and large area compatible as compared to rigid substrates. However, during fabrication and service they are subjected to complex strains, resulting in crack formation or delamination within the layers, affecting the device performance. Therefore, it is necessary to understand their failure mechanisms by correlating their electrical or structural properties with applied strain, supported by detailed microstructural investigations

Doped And Chemically Transformed Transition Metal Dichalcogenides (tmdcs) For Two-Dimensional (2d) Electronics

Transition metal dichalcogenides (TMDCs) as the semiconductor counterparts of gra-phene have emerged as promising channel materials for flexible electronic and optoelectronic devices. The 2D layer structure of TMDCs enables the ultimate scaling of TMDC-based devices down to atomic thickness. Furthermore, the absence of dangling bonds in these materials helps to form high quality heterostructures with ultra-clean interfaces. The main objective of this work is to develop novel approaches to fabricating TMDC-based 2D electronic devices such as diodes and transistors. In the first part, we have fabricated 2D p-n junction diodes through van der Waals assembly of heavily p-doped MoS2 (WSe2) and lightly n-doped MoS2 to form vertical homo-(hetero-) junctions, which allows to continuously tune the electron concentration on the n-side for a wide range. In sharp contrast to conventional p-n junction diodes, we have observed nearly exponential dependence of the reverse-current on gate-voltage in our 2D p-n junction devices, which can be attributed to band-to-band tunneling through a gate-tunable tunneling barrier. In the second part, we developed a new strategy to engineer high-κ dielectrics by con-verting atomically thin metallic 2D TMDCs into high-κ dielectrics because it remains a signifi-cant challenge to deposit uniform high-κ dielectric thin films on TMDCs with ALD due to the lack of dangling bonds on the surfaces of TMDCs. In our study, we converted mechanically ex-foliated atomically thin layers of a 2D metal, TaS2 (HfSe2) into a high-κ dielectric, Ta2O5 (HfO2) by thermal oxidation. X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), energy dispersive spectroscopy (EDS), and atomic force microscopy (AFM) were used to understand the phase conversion process. Capacitance-voltage (C-V) measure-ments were carried out to determine the dielectric constant of thermally oxidized dielec-trics. We fabricated MoS2 field-effect transistors (FETs) with thermally oxidized ultra-thin and ultra-smooth Ta2O5 as top-gate and bottom-gate high-κ dielectric layers. We observed promis-ing device performance, including a nearly ideal subthreshold swing of ~ 61 mV/dec at room temperature, negligible hysteresis, drain-current saturation in the output characteristics, a high on/off ratio ~ 106, and a room temperature field-effect mobility exceeding 60 cm2/Vs. To fur-ther reduce the leak current and improve the device performance, we have also investigated the chemical transformation of HfSe2 to HfO2 high-κ dielectric, which has significantly larger band gap than Ta2O5

A study of the electrical properties of polycrystalline based organic devices

In this thesis, examination of polycrystalline organic based devices such as the Schottky diode and MOS capacitor is carried out. The data is interpreted in terms of a polycrystalline model based mainly on a conventional polysilicon model with slight modifications to fit the organic properties. A brief introduction to the existing charge transport models for organic materials is presented. The most dominant being the variable range hopping model for disordered materials. The disorder analysis is appropriate in the grain boundaries of a polycrystalline material. The distribution of the traps of density of states (DOS) is commonly described by the Gaussian distribution and the associated exponential approximate at low energies. This is a valid assumption for organic semiconductors with low carrier mobility values [N. Sedghi et al., J. Non Crys. Solids 352, 1641, 2006]. Detailed investigation on the temperature effects of the polycrystalline Schottky diode leads to determination of important electrical parameters. Such studies are essential in understanding the conduction processes of the organic device, particularly in terms of trapping effects, which is essential in the development of device models for organic circuitry. Several parameters such as dopant (ND) and carrier concentrations (p), effective mobility (μeff), depletion width (Wdep), effective Debye length (LDe), Meyer Neldel energy (MNE) and the characteristic temperature of the carriers (T0) are extracted from the current-voltage characteristics of the diode. For a soluble derivative of pentacene, 6, 13-triisopropylsilyethynyl pentacene (TIPS) blended with Polytriarylamine (PTAA), the respective values extracted at room temperature are found to be approximately 1017 cm-3, 1.8x10-2 cm2V-1s-1, 185 nm, 11 nm, 31.5 meV and 780 K, respectively. As the temperature falls, the values of most parameters remain constant until a critical temperature. The activation energy also remains constant at approximately 0.3 eV for various applied voltages in saturation. Below this critical temperature, Wdep, LDe and T0 increase whilst μeff, ND/p and characteristic temperature of the states (TC) decrease. Similar analysis is carried out on doped layers of TIPS with a different insulating binder Poly-alpha methylstyrene (PAMS). The value of Wdep, LDe, T0, μeff, ND/p, MNE and TC obtained from such doped Schottky diode are approximately 100 nm, 5 nm, 1200 K, 1x10-2 cm2V-1s-1, 2x1017 cm-3, 35 meV and 400 K, respectively. The Capacitance-Voltage (C-V) analysis on polycrystalline Schottky diodes provides ND of approximately 7.6 x 1016 cm-3, 5.2 x 1014 cm-3 and 2.98 x 1014cm-3 at 500 Hz, 1 kHz and 2 kHz respectively. These ND values are lower than those extracted from current-voltage characteristics and decrease with increasing frequency. This is thought to be due to the low mobility of holes, unable to respond to the signal at higher frequencies. The conduction in polycrystalline organic Schottky diode is proposed using a 2-dimensional (2D) model, which focuses on both the lateral and vertical conduction paths. The organic semiconductor layer is assumed to be relatively thin so that only a single layer of the grain exists between adjacent grain boundaries for the vertical conduction. A two dimensional situation is treated as two separate one dimensional problems that are positioned at right angles to each other. The grain and grain boundaries in the polycrystalline material are explained in terms of two boundary conditions. The variation of potential in grain boundary is the basis in defining the variation of potential in the grains. Conduction under forward bias in the grain and grain boundary is thus established assuming two distributions for the DOS, namely the Gaussian and Laplace. In comparison, Laplace DOS is believed to be a better representation of the distribution of states, where a large number of energy levels are being scanned with applied voltage. The ac properties of a polycrystalline based MOS capacitor are investigated. The frequency and temperature effects on the C-V characteristics of MOS capacitor based on another soluble derivative of pentacene, refered here as S1150, are studied. Equivalent circuits which include the effects of bulk and series resistance due to contact effects are analysed. The bulk resistance (Rb), bulk capacitance (Cb) and series resistance (RS) are found to be approximately 13 kΩ, 760 pF and less than 309 Ω respectively, for an organic film thickness (tOSC) of 27nm. For ND ≈ 3.6 x 1017cm-3 at 1 kHz, the hole mobility is found to be approximately 4.6x10-7cm2V-1s-1. As expected the mobility decreases with increase in frequency. Furthermore, the temperature study of inverse square space charge capacitance (1/CS2) against absolute temperature (T) provides an intercept close to T (~ 330K) instead of TC. A low intercept value indicates a decrease in disorder which suggests that the large grains may be dominating the capacitance

Novel Materials for Post-Silicon Electronics: 2D Semiconductors, Perovskite Dielectrics, and Metal-Organic Frameworks

Over the past five decades, the progress of scaling down metal-oxide-semiconductor field-effect transistors (MOSFETs) has been the main reason for boosting the performance of most electronic products we use. However, ultrascaled MOSFETs suffer from many issues related to fundamental quantum limitations imposed by extreme minification. Two main strategies are proposed to address these problems: (1) The first one is to pile electronic device layers that can compute data vertically, i.e., 3D integration; hence more operations can be implemented in the same area. 3D integration considerably relies on the back-end-of-line (BEOL) process, where dense metal interconnects result in the aggravated resistive-capacitive (RC) delay. To solve this problem, new low-κ gap-filling materials are required. Metal-organic frameworks (MOFs) are emerging coordination compounds consisting of metal ion nodes connected by organic linkers with repeating coordination. The rigid ionic bonds and orderly porous structures give MOFs particular mechanical strength and low permittivity to be a potential candidate. In addition, designable functionality enables MOF to serve as versatile active components. However, major preparations for MOF coatings are solution-based routes, making them incompatible with advanced semiconductor fabrications whose features are getting smaller and deeper. (2) Another strategy is implementing low-dimensional semiconductors to replace silicon as the transistor channel because of their talent for being atomically thin without degrading performance. Although 2D transition metal dichalcogenides (TMDCs) are recognized as the most promising among several candidates, there are still a number of challenges to be addressed before practically adopting them in the industry. In this thesis, a low-temperature chemical vapor deposition (CVD) synthetic method of MOFs is demonstrated, which can be implemented as low-κ gap-filling materials in increasingly important BEOL processes and active material in chemical sensors. Furthermore, this thesis exhibits the integration of single-crystal SrTiO3 gate dielectric in the monolayer CVD MoS2 FETs. The high-permittivity natural of SrTiO3 facilitates the gate controllability for ultrascaled transistors. The devices manifest good reliability and competitive performance characteristics, including a steep subthreshold swing (SS) of 70 mV/dec and a large ON/OFF current ratio of 1E7

Germanium MOSFETs with high-K gate dielectric and advanced source/drain structure

Ph.DDOCTOR OF PHILOSOPH

Characterization and compact modeling of printed electrolyte-gated thin film transistors and circuits

Die Herstellung konventioneller Elektronik ist ein hochkomplexer Prozess, der hohe Kosten erfordert. In diesem Zusammenhang gewinne die gedruckte Elektronik sowohl in der Wissenschaft als auch in der Industrie eine erhöhte Aufmerksamkeit. Der Hauptgrund dafür ist die Vereinfachung des Herstellungsprozesses durch additive Drucktechnologien wie Inkjet-Druck. Dies hat Vorteile wie die bedarfsgerechte Herstellung und minimaler Materialverbrauch. Außerdem wird eine vielfältige Auswahl verschiedener Substratmaterialien ermöglicht. Im Zentrum der Entwicklung von Schaltungen auf Basis gedruckter Elektronik stehen gedruckte Transistoren. In letzter Zeit sind Metalloxidhalbleiter wie Indiumoxid aufgrund ihrer hohen Ladungsbeweglichkeit zu vielversprechenden Materialien für die Herstellung gedruckter elektronischer Bauelemente geworden. Darüber hinaus bietet der Elektrolyt-Gate-Ansatz aufgrund der großen Gate-Kapazität, die durch die elektrischen Doppelschichten bereitgestellt wird, auch die Vorteile, einen Niederspannungsbetrieb im Sub-1 V-Bereich zu erreichen. Dies eröffnet neue Möglichkeiten für die Herstellung gedruckter Bauteile und Schaltungen in Nischenanwendungen. Um das Design und die Herstellung von gedruckten Schaltungen zu erleichtern, ist die Entwicklung kompakter Modelle erforderlich. Die meisten existierenden Arbeiten haben sich bisher auf die Untersuchung des statischen Verhaltens von Transistoren konzentriert. Hierbei wird das dynamische und das Rauschverhalten der Bauteile häufig vernachlässigt. Ziel dieser Arbeit ist es daher, die umfassende Untersuchung der Kapazitäts sowie Rauscheigenschaften Tintenstrahl-gedruckter Dünnschichttransistoren mit einem flüssig-prozessierbaren Feststoffelektrolyten als Isolator (EGT) und einem Indiumoxid-Halbleiter als Kanalmaterial durchzuführen.. Es werden geeignete Modellierungsansätze vorgeschlagen, um das elektrische Verhalten genau zu erfassen. Dies ermöglicht eine erweiterte Analyse analoger, digitaler sowie gemischter analog-digitaler Schaltungen. In dieser Arbeit wird die Kapazität von EGTs mittels spannungsabhängiger Impedanzspektroskopie charakterisiert. Intrinsische und extrinsische Effekte werden durch Verwendung von De-Embedding-Teststrukturen getrennt. Des Weiteren wird ein Ersatzschaltbild erstellt, um genaue Simulationen des gemessenen Frequenzgangs der Gate-Impedanz zu ermöglichen. Auf dieser Grundlage zeigt sich, dass Top-Gate EGTs das Potenzial haben, eine Schaltfrequenz im kHz-Bereich zu erreichen, wenn die Materialien und der Druckprozess weiter optimiert werden. Darüber hinaus wird ein Meyer-ähnliches Modell vorgeschlagen, um die Kapazitäts-Spannungs-Eigenschaften der Anschlusskapazität genau zu erfassen. Es werden sowohl parasitäre Kapazitäten als auch nicht-quasistatische Effekte berücksichtigt. Die resultierenden Modelle ermöglichen weitere AC- und transiente Simulationen komplexer Schaltungen in der EGT-Technologie. Im Folgenden werden Untersuchungen zu den Rauscheigenschaften gedruckter EGTs durchgeführt. Das Niederfrequenzrauschen wird anhand eines eigens dafür optimierten Versuchsaufbaus charakterisiert. Durch Untersuchung der gemessenen Rauschspektren im Transistor-Drainstrom bei verschiedenen Gate-Spannungen wurde die Ladungsträgerschwankung mit korrelierter Mobilitätsschwankung als primärer Rauschmechanismus bestimmt. Auf dieser Grundlage kann das normalisierte Flachband-Spannungsrauschen als Hauptleistungsmetrik berechnet werden, was im Vergleich zu anderen Dünnschichttechnologien, die auf Dielektrika und Halbleitern wie IZO und IGZO basieren, einen erheblich niedrigeren Wert aufweist.. Ein plausibler Grund könnte die große Gate-Kapazität sein, die durch die elektrische Doppelschicht erzeugt wird. Daher eigenen sich gedruckte EGTs für beispielsweise rauscharme Anwendungen in der Sensorik. Abschließend werden verschiedene Schaltungsdesigns vorgeschlagen, die auf EGT-Technologie basieren. Dies beinhaltet grundlegende digitale Schaltungen wie Inverter Strukturen und Ringoszillatoren. Ihre Leistungsmetriken, einschließlich der Gatterlaufzeit und dem Stromverbrauch, werden ausführlich charakterisiert. Des Weiteren wird das erste Design eines gedruckten Brückengleichrichters unter Verwendung von EGTs mit eine nahe-null-Volt-Schwellspannung in einer Dioden-Konfiguration vorgestellt. Der vorgestellte Gleichrichter ist in der Lage, Eingangsspannungen mit kleiner Amplitude von circa 100 mV effektiv zu verarbeiten. Dies ist besonders im Anwendungsbereich des Energy-Harvestings von Interesse. Zusätzlich werden die zuvor etablierten Kapazitätsmodelle auf diesen Schaltungen verifiziert. Ein Vergleich der Simulations- und Messdaten zeigt deren sehr gute Übereinstimmung und verifiziert die entwickelten Kapazitätsmodelle