Electrical performance analysis of high-speed interconnects and circuits by numerical modeling methods

Ph.DDOCTOR OF PHILOSOPH

Passivity Enforcement via Perturbation of Hamiltonian Matrices

This paper presents a new technique for the passivity enforcement of linear time-invariant multiport systems in statespace form. This technique is based on a study of the spectral properties of related Hamiltonian matrices. The formulation is applicable in case the system input-output transfer function is in admittance, impedance, hybrid, or scattering form. A standard test for passivity is first performed by checking the existence of imaginary eigenvalues of the associated Hamiltonian matrix. In the presence of imaginary eigenvalues the system is not passive. In such a case, a new result based on first-order perturbation theory is presented for the precise characterization of the frequency bands where passivity violations occur. This characterization is then used for the design of an iterative perturbation scheme of the state matrices, aimed at the displacement of the imaginary eigenvalues of the Hamiltonian matrix. The result is an effective algorithm leading to the compensation of the passivity violations. This procedure is very efficient when the passivity violations are small, so that first-order perturbation is applicable. Several examples illustrate and validate the procedure

Simulation for Reliability, Hardware Security, and Ising Computing in VLSI Chip Design

The continued scaling of VLSI circuits has provided a wealth of opportunities andchallenges to the VLSI circuit design area. Both these challenges and opportunities, however,require new simulation tools that can enable their solution or exploitation as classicalmethods typically dealt with problem domains with smaller scales or less complexity. Inthis dissertation, simulation methods are presented to address the emerging VLSI designtopics of Electromigration induced aging and Ising computing and are then applied to theapplication areas of hardware security and graph partitioning respectively.The Electromigration aging effect in VLSI circuits is a long-term reliability issueaffecting current carrying metal wires leading to IR drop degradation. Typically, simpleanalytical equations can determine a wire’s effective age or if it will be affected by the EMaging effect at all. However, these classical methods are overly conservative and can lead toover design or unnecessary design iterations. Furthermore, it is expected that the EM agingeffect will become more severe in future Integrated Cirucits (ICs) due to increasing currentdensities and the prevalance of polycrystaline copper atom structures seen at small wiredimensions. For this reason, more comprehensive simulation techniques that can efficientlysimulate the EM effect with less conservative results can help mitigate overdesign andincrease design margins while reducing design iterations.The area of Hardware Security is becoming increasingly important as the chipsupply chain becomes more globalized and the integrity of chips becomes more diffiuclt toverify. Utilizing the accurate simulation techniques for EM, we can utilize this reliabilityeffect to demonstrate how a reliability based attack could be perpatrated. Furthermore, wecan utilize this aging effect as a defense mechanism to help us validate the integrity of anIC and detect counterfeit chips in the component supply chain market.Ising computing is an emerging method of solving combinatorial optimization problemsby simulating the interactions of so-called spin glasses and their interactions. Borrowingconcepts from quantum computing, this methods mimics the quantum interaction betweenspin glasses in such a way that finding a ground state of these spin glass models leadsto the solution of a particular problem. In this dissertation, effective methods of simulatingthe spin glass interactions using General Purpose Graphics Processing Units (GPGPUs)and finding their ground state are developed.In addition to the GPU based Ising model simulations, important combinatorialproblems can be mapped to the Ising model. In this dissertation the Ising solver is appliedto graph partitioning which can be utilized in VLSI design and many other domains as well.Specifically, solvers for the maxcut problem and the balanced min-cut partitioning problemare developed

Interpolation-based parameterized model order reduction of delayed systems

Three-dimensional electromagnetic methods are fundamental tools for the analysis and design of high-speed systems. These methods often generate large systems of equations, and model order reduction (MOR) methods are used to reduce such a high complexity. When the geometric dimensions become electrically large or signal waveform rise times decrease, time delays must be included in the modeling. Design space optimization and exploration are usually performed during a typical design process that consequently requires repeated simulations for different design parameter values. Efficient performing of these design activities calls for parameterized model order reduction (PMOR) methods, which are able to reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as layout or substrate features. We propose a novel PMOR method for neutral delayed differential systems, which is based on an efficient and reliable combination of univariate model order reduction methods, a procedure to find scaling and frequency shifting coefficients and positive interpolation schemes. The proposed scaling and frequency shifting coefficients enhance and improve the modeling capability of standard positive interpolation schemes and allow accurate modeling of highly dynamic systems with a limited amount of initial univariate models in the design space. The proposed method is able to provide parameterized reduced order models passive by construction over the design space of interest. Pertinent numerical examples validate the proposed PMOR approach

Physics-based passivity-preserving parameterized model order reduction for PEEC circuit analysis

The decrease of integrated circuit feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods, and model order reduction (MOR) methods have proven to be very effective in combating such high complexity. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the circuit under study as a function of design parameters such as geometrical and substrate features. Traditional MOR techniques perform order reduction only with respect to frequency, and therefore the computation of a new electromagnetic model and the corresponding reduced model are needed each time a design parameter is modified, reducing the CPU efficiency. Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as geometrical layout or substrate characteristics. We propose a novel PMOR technique applicable to PEEC analysis which is based on a parameterization process of matrices generated by the PEEC method and the projection subspace generated by a passivity-preserving MOR method. The proposed PMOR technique guarantees overall stability and passivity of parameterized reduced order models over a user-defined range of design parameter values. Pertinent numerical examples validate the proposed PMOR approach

Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect

This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an alternative to the existing Cu-based interconnect for post-CMOS technology nodes with an emphasis on thermal stability. Starting from the material modeling, this work includes material characterization, exploration of electronic properties, vibrational properties and to analyze performance as a VLSI interconnect. Using state of the art density functional theories (DFT) one-dimensional and two-dimensional materials were designed for exploring their electronic structures, transport properties and their circuit behaviors. Primarily carbon nanotube (CNT), graphene and graphene/copper based interconnects were studied in this work. Being reduced dimensional materials the charge carriers in CNT(1-D) and in graphene (2-D) are quantum mechanically confined as a result of this free electron approximation fails to explain their electronic properties. For same reason Drude theory of metals fails to explain electronic transport phenomena. In this work Landauer transport theories using non-equilibrium Green function (NEGF) formalism was used for carrier transport calculation. For phonon transport studies, phenomenological Fourier’s heat diffusion equation was used for longer interconnects. Semi-classical BTE and Landauer transport for phonons were used in cases of ballistic phonon transport regime. After obtaining self-consistent electronic and thermal transport coefficients, an equivalent circuit model is proposed to analyze interconnects’ electrical performances. For material studies, CNTs of different variants were analyzed and compared with existing copper based interconnects and were found to be auspicious contenders with integrational challenges. Although, Cu based interconnect is still outperforming other emerging materials in terms of the energy-delay product (1.72 fJ-ps), considering the electromigration resistance graphene Cu hybrid interconnect proposed in this dissertation performs better. Ten times more electromigration resistance is achievable with the cost of only 30% increase in energy-delay product. This unique property of this proposed interconnect also outperforms other studied alternative materials such as multiwalled CNT, single walled CNT and their bundles

Doctor of Philosophy

dissertationRecent breakthroughs in silicon photonics technology are enabling the integration of optical devices into silicon-based semiconductor processes. Photonics technology enables high-speed, high-bandwidth, and high-fidelity communications on the chip-scale-an important development in an increasingly communications-oriented semiconductor world. Significant developments in silicon photonic manufacturing and integration are also enabling investigations into applications beyond that of traditional telecom: sensing, filtering, signal processing, quantum technology-and even optical computing. In effect, we are now seeing a convergence of communications and computation, where the traditional roles of optics and microelectronics are becoming blurred. As the applications for opto-electronic integrated circuits (OEICs) are developed, and manufacturing capabilities expand, design support is necessary to fully exploit the potential of this optics technology. Such design support for moving beyond custom-design to automated synthesis and optimization is not well developed. Scalability requires abstractions, which in turn enables and requires the use of optimization algorithms and design methodology flows. Design automation represents an opportunity to take OEIC design to a larger scale, facilitating design-space exploration, and laying the foundation for current and future optical applications-thus fully realizing the potential of this technology. This dissertation proposes design automation for integrated optic system design. Using a buildingblock model for optical devices, we provide an EDA-inspired design flow and methodologies for optical design automation. Underlying these flows and methodologies are new supporting techniques in behavioral and physical synthesis, as well as device-resynthesis techniques for thermal-aware system integration. We also provide modeling for optical devices and determine optimization and constraint parameters that guide the automation techniques. Our techniques and methodologies are then applied to the design and optimization of optical circuits and devices. Experimental results are analyzed to evaluate their efficacy. We conclude with discussions on the contributions and limitations of the approaches in the context of optical design automation, and describe the tremendous opportunities for future research in design automation for integrated optics