Epälineaarinen vääristymä laajakaistaisissa analogia-digitaalimuuntimissa

This thesis discusses nonlinearities of analog-to-digital converters (ADCs) and their mitigation using digital signal processing (DSP). Particularly wideband radio receivers are considered here including, e.g., the emerging cognitive radio applications. In this kind of receivers, a single ADC converts a mixture of signals at different frequency bands to digital domain simultaneously. Different signals may have considerably different power levels and hence the overall dynamic range can be very large (even 50–60 dB). Therefore, even the smallest ADC nonlinearities can produce considerable amount of nonlinear distortion, which may cause a strong signal to block significantly weaker signal bands. One concrete source of nonlinear distortion is waveform clipping due to improper signal conditioning in the input of an ADC. In the thesis, a mathematical model for this phenomenon is derived through Fourier analysis and is then used as a basis for an adaptive interference cancellation (AIC) method. This is a general method for reducing nonlinear distortion and besides clipping it can be used, e.g., to compensate integral nonlinearity (INL) originating from unintentional deviations of the quantization levels. Additionally, an interpolation method is proposed in this thesis to restore clipped waveforms and hence reduce nonlinear distortion. Through several computer simulations and corresponding laboratory radio signal measurements, the performance of the proposed post-processing methods is illustrated. It can be seen from the results that the methods are able to reduce nonlinear distortion from a weak signal band in a considerable manner when there are strong blocking signals in the neighboring channels. According to the results, the AIC method would be a highly recommendable post-processing technique for modern radio receivers due to its general ability to reduce nonlinear distortion regardless of its source. /Kir10Tässä työssä käsitellään analogia-digitaalimuuntimien (AD-muuntimien) epälineaarisuuksia ja niiden lieventämistä digitaalisen signaalinkäsittelyn (DSP) avulla. Tätä on tarkasteltu erityisesti laajakaistaisten radiovastaanottimien näkökulmasta, joka käsittää mm. tulevat kognitiiviseen radioon liittyvät sovellukset. Tällaisissa vastaanottimissa yksittäinen AD-muunnin muuntaa samanaikaisesti useita eri taajuuskaistoilla olevia signaaleita digitaaliseen muotoon, jolloin yhteenlaskettu dynaaminen alue voi olla hyvin suuri (jopa 50–60 dB). Tämän takia AD-muuntimen pienimmätkin epälineaarisuudet voivat aiheuttaa huomattavasti epälineaarista vääristymää, minkä vuoksi voimakas signaali saattaa häiriöllään peittää muilla taajuuskaistoilla olevia selkeästi heikompia signaaleja. Eräs konkreettinen epälineaarisen vääristymän aiheuttaja on aaltomuodon leikkaantuminen AD-muuntimen sisäänmenossa jännitealueen ylittymisen vuoksi. Tässä työssä johdetaan matemaattinen malli kyseiselle ilmiölle Fourier-analyysin avulla ja käytetään sitä lähtökohtana adaptiiviselle häiriönpoistomenetelmälle (AIC-menetelmä). Se on yleisluonteinen menetelmä epälineaarisen vääristymän vähentämiseksi, ja leikkaantumisen lisäksi sitä voidaan käyttää esimerkiksi kompensoimaan integraalista epälineaarisuutta (INL), joka on peräisin kvantisointitasojen tahattomista poikkeamista. Lisäksi tässä työssä esitellään interpolointimenetelmä leikkaantuneen aaltomuodon ehostamiseen siten, että epälineaarinen häiriö vähenee. Esiteltyjen jälkikäsittelymenetelmien suorituskykyä analysoidaan ja havainnollistetaan useilla tietokonesimulaatiolla sekä niitä vastaavilla radiosignaalien laboratoriomittauksilla. Tuloksista voidaan nähdä, että nämä menetelmät kykenevät poistamaan huomattavasti epälineaarista vääristymää heikolta signaalikaistalta silloin, kun naapurikaistoilla on voimakkaita häiriösignaaleja. Tulosten perusteella AIC-menetelmä olisi erittäin suositeltava jälkikäsittelytekniikka moderneihin radiovastaanottimiin, koska se pystyy yleisesti vähentämään epälineaarista vääristymää riippumatta häiriön alkuperästä

System-Level Design of All-Digital LTE / LTE-A Transmitter Hardware

This thesis presents a detailed system-level analysis of an all-digital transmitter hardware based on the Direct-Digital RF-Modulator (DDRM). The purpose of the presented analysis is to evaluate whether this particular transmitter architecture is suitable to be used in LTE / LTE-A mobile phones. The DDRM architecture is based on the Radio Frequency Digital-to-Analog Converter (RF-DAC), whose system-level characteristics are investigated in this work through mathematical analysis and MATLAB simulations. In particular, a new analytical model for the timing error in the distributed upconversion is developed and verified. Moreover, this thesis reviews the LTE and LTE-A standards, and describes how a baseband environment for signal generation/demodulation can be implemented in MATLAB. The presented system enables much more flexibility with respect to current commercial softwares like Agilent Signal Studio. Simulation results show that the most challenging specification to meet is the out-of-band noise floor, because of the stringent linearity and timing requirements posed on the RF-DAC. This suggests that new means of reducing the out-of-band noise in all-digital transmitters should be researched, in order not to make their design more complicated than for their analog counterpart

Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers

The quest for multi-standard and software-defined radio (SDR) receivers calls for high flexibility in the receiver building-blocks so that to accommodate several wireless services using a single receiver chain in mobile handsets. A potential approach to achieve flexibility in the receiver is to move the analog-to-digital converter (ADC) closer to the antenna so that to exploit the enormous advances in digital signal processing, in terms of technology scaling, speed, and programmability. In this context, continuous-time (CT) delta-sigma (ΔƩ) ADCs show up as an attractive option. CT ΔƩ ADCs have gained significant attention in wideband receivers, owing to their amenability to operate at a higher-speed with lower power consumption compared to discrete-time (DT) implementations, inherent anti-aliasing, and robustness to sampling errors in the loop quantizer. However, as the ADC moves closer to the antenna, several blockers and interferers are present at the ADC input. Thus, it is important to investigate the sensitivities of CT ΔƩ ADCs to out-of-band (OOB) blockers and find the design considerations and solutions needed to maintain the performance of CT ΔƩ modulators in presence of OOB blockers. Also, CT ΔƩ modulators suffer from a critical limitation due to their high sensitivity to the clock-jitter in the feedback digital-to-analog converter (DAC) sampling-clock. In this context, the research work presented in this thesis is divided into two main parts. First, the effects of OOB blockers on the performance of CT ΔƩ modulators are investigated and analyzed through a detailed study. A potential solution is proposed to alleviate the effect of noise folding caused by intermodulation between OOB blockers and shaped quantization noise at the modulator input stage through current-mode integration. Second, a novel DAC solution that achieves tolerance to pulse-width jitter by spectrally shaping the jitter induced errors is presented. This jitter-tolerant DAC doesn’t add extra requirements on the slew-rate or the gain-bandwidth product of the loop filter amplifiers. The proposed DAC was implemented in a 90nm CMOS prototype chip and provided a measured attenuation for in-band jitter induced noise by 26.7dB and in-band DAC noise by 5dB, compared to conventional current-steering DAC, and consumes 719µwatts from 1.3V supply

Nonlinear Distortion in Wideband Radio Receivers and Analog-to-Digital Converters: Modeling and Digital Suppression

Emerging wireless communications systems aim to flexible and efficient usage of radio spectrum in order to increase data rates. The ultimate goal in this field is a cognitive radio. It employs spectrum sensing in order to locate spatially and temporally vacant spectrum chunks that can be used for communications. In order to achieve that, flexible and reconfigurable transceivers are needed. A software-defined radio can provide these features by having a highly-integrated wideband transceiver with minimum analog components and mostly relying on digital signal processing. This is also desired from size, cost, and power consumption point of view. However, several challenges arise, from which dynamic range is one of the most important. This is especially true on receiver side where several signals can be received simultaneously through a single receiver chain. In extreme cases the weakest signal can be almost 100 dB weaker than the strongest one. Due to the limited dynamic range of the receiver, the strongest signals may cause nonlinear distortion which deteriorates spectrum sensing capabilities and also reception of the weakest signals. The nonlinearities are stemming from the analog receiver components and also from analog-to-digital converters (ADCs). This is a performance bottleneck in many wideband communications and also radar receivers. The dynamic range challenges are already encountered in current devices, such as in wideband multi-operator receiver scenarios in mobile networks, and the challenges will have even more essential role in the future.This thesis focuses on aforementioned receiver scenarios and contributes to modeling and digital suppression of nonlinear distortion. A behavioral model for direct-conversion receiver nonlinearities is derived and it jointly takes into account RF, mixer, and baseband nonlinearities together with I/Q imbalance. The model is then exploited in suppression of receiver nonlinearities. The considered method is based on adaptive digital post-processing and does not require any analog hardware modification. It is able to extract all the necessary information directly from the received waveform in order to suppress the nonlinear distortion caused by the strongest blocker signals inside the reception band.In addition, the nonlinearities of ADCs are considered. Even if the dynamic range of the analog receiver components is not limiting the performance, ADCs may cause considerable amount of nonlinear distortion. It can originate, e.g., from undeliberate variations of quantization levels. Furthermore, the received waveform may exceed the nominal voltage range of the ADC due to signal power variations. This causes unintentional signal clipping which creates severe nonlinear distortion. In this thesis, a Fourier series based model is derived for the signal clipping caused by ADCs. Furthermore, four different methods are considered for suppressing ADC nonlinearities, especially unintentional signal clipping. The methods exploit polynomial modeling, interpolation, or symbol decisions for suppressing the distortion. The common factor is that all the methods are based on digital post-processing and are able to continuously adapt to variations in the received waveform and in the receiver itself. This is a very important aspect in wideband receivers, especially in cognitive radios, when the flexibility and state-of-the-art performance is required

Linear Precoding with Low-Resolution DACs for Massive MU-MIMO-OFDM Downlink

We consider the downlink of a massive multiuser (MU) multiple-input multiple-output (MIMO) system in which the base station (BS) is equipped with low-resolution digital-to-analog converters (DACs). In contrast to most existing results, we assume that the system operates over a frequency-selective wideband channel and uses orthogonal frequency division multiplexing (OFDM) to simplify equalization at the user equipments (UEs). Furthermore, we consider the practically relevant case of oversampling DACs. We theoretically analyze the uncoded bit error rate (BER) performance with linear precoders (e.g., zero forcing) and quadrature phase-shift keying using Bussgang's theorem. We also develop a lower bound on the information-theoretic sum-rate throughput achievable with Gaussian inputs, which can be evaluated in closed form for the case of 1-bit DACs. For the case of multi-bit DACs, we derive approximate, yet accurate, expressions for the distortion caused by low-precision DACs, which can be used to establish lower bounds on the corresponding sum-rate throughput. Our results demonstrate that, for a massive MU-MIMO-OFDM system with a 128-antenna BS serving 16 UEs, only 3--4 DAC bits are required to achieve an uncoded BER of 10^-4 with a negligible performance loss compared to the infinite-resolution case at the cost of additional out-of-band emissions. Furthermore, our results highlight the importance of taking into account the inherent spatial and temporal correlations caused by low-precision DACs

Design, analysis and evaluation of sigma-delta based beamformers for medical ultrasound imaging applications

The inherent analogue nature of medical ultrasound signals in conjunction with the abundant merits provided by digital image acquisition, together with the increasing use of relatively simple front-end circuitries, have created considerable demand for single-bit beamformers in digital ultrasound imaging systems. Furthermore, the increasing need to design lightweight ultrasound systems with low power consumption and low noise, provide ample justification for development and innovation in the use of single-bit beamformers in ultrasound imaging systems. The overall aim of this research program is to investigate, establish, develop and confirm through a combination of theoretical analysis and detailed simulations, that utilize raw phantom data sets, suitable techniques for the design of simple-to-implement hardware efficient digital ultrasound beamformers to address the requirements for 3D scanners with large channel counts, as well as portable and lightweight ultrasound scanners for point-of-care applications and intravascular imaging systems. In addition, the stability boundaries of higher-order High-Pass (HP) and Band-Pass (BP) Σ−Δ modulators for single- and dual- sinusoidal inputs are determined using quasi-linear modeling together with the describing-function method, to more accurately model the modulator quantizer. The theoretical results are shown to be in good agreement with the simulation results for a variety of input amplitudes, bandwidths, and modulator orders. The proposed mathematical models of the quantizer will immensely help speed up the design of higher order HP and BP Σ−Δ modulators to be applicable for digital ultrasound beamformers. Finally, a user friendly design and performance evaluation tool for LP, BP and HP modulators is developed. This toolbox, which uses various design methodologies and covers an assortment of modulators topologies, is intended to accelerate the design process and evaluation of modulators. This design tool is further developed to enable the design, analysis and evaluation of beamformer structures including the noise analyses of the final B-scan images. Thus, this tool will allow researchers and practitioners to design and verify different reconstruction filters and analyze the results directly on the B-scan ultrasound images thereby saving considerable time and effort

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Ultra Low Power Amplification and Digitization System for Neural Signal Recording Applications

The scope is to develop a tunable low power fully integrated bandpass filter and a low power second order sigma-delta ADC modulator for implantable neural signal amplification and digitization applications, with subthreshold circuit design techniques in different CMOS processes. Since biopotentials usually contain low frequency components, the neural filters in this project have to be able to achieve large and predictable time constant for implantable applications. Voltage biased pseudo-resistors are vulnerable to process variations and circuit imperfections, and hence not suitable for implantable applications. A current biased pseudo-resistor is implemented in the neural filters in this work to set the cutoff frequency, and a Taylor series is used to study its linearity. The filters with proposed current biased pseudo-resistors were fabricated in two different CMOS processes and tested. The test results verify that the filters with current biased pseudo-resistors are tunable, and not vulnerable to process variations and circuit imperfections. The filters with current biased pseudo-resistors meet the design requirements of fully integrated, implantable applications. The sigma-delta ADC modulator was designed and simulated in a half micron SOS CMOS process. The simulation results of the ADC confirm the possibility of an ultra low power ADC for neural signal recording applications.School of Electrical & Computer Engineerin