3D Capacitance Extraction With the Method of Moments

In this thesis, the Method of Moments has been applied to calculate capacitance between two arbitrary 3D metal conductors or a capacitance matrix for a 3D multi-conductor system. Capacitance extraction has found extensive use for systems involving sets of long par- allel transmission lines in multi-dielectric environment as well as integrated circuit package including three-dimensional conductors located on parallel planes. This paper starts by reviewing fundamental aspects of transient electro-magnetics followed by the governing dif- ferential and integral equations to motivate the application of numerical methods as Method of Moments(MoM), Finite Element Method(FEM), etc. Among these numerical tools, the surface-based integral-equation methodology - MoM is ideally suited to address the prob- lem. It leads to a well-conditioned system with reduced size, as compared to volumetric methods. In this dissertation, the MoM Surface Integral Equation (SIE)-based modeling approach is developed to realize electrostatic capacitance extraction for 3D geometry. MAT- LAB is employed to validate its e?ciency and e?ectiveness along with design of a friendly GUI. As a base example, a parallel-plate capacitor is considered. We evaluate the accu- racy of the method by comparison with FEM simulations as well as the corresponding quasi-analytical solution. We apply this method to the parallel-plate square capacitor and demonstrate how far could the undergraduate result 0C = A ? =d\u27 be from reality. For the completion of the solver, the same method is applied to the calculation of line capacitance for two- and multi-conductor 2D transmission lines

Interconnect capacitance extraction under geometric uncertainties

Interconnects are an important constituent of any large scale integrated circuit, and accurate interconnect analysis is essential not only for post-layout verification but also for synthesis. For instance, extraction of interconnect capacitance is needed for the prediction of interconnect-induced delay, crosstalk, and other signal distortion related effects that are used to guide IC routing and floor planning. The continuous progress of semiconductor technology is leading ICs to the era of 45 nm technology and beyond. However, this progress has been associated with increasing variability during the manufacturing processes. This variability leads to stochastic variations in geometric and material parameters and has a significant impact on interconnect capacitance. It is therefore important to be able to quantify the effect of such process induced variations on interconnect capacitance. In this thesis, we have worked on a methodology towards modeling of interconnect capacitance in the presence of geometric uncertainties. More specifically, a methodology is proposed for the finite element solution of Laplace's equation for the calculation of the per-unit-length capacitance matrix of a multi-conductor interconnect structure embedded in a multi-layered insulating substrate and in the presence of statistical variation in conductor and substrate geometry. The proposed method is founded on the idea of defining a single, mean geometry, which is subsequently used with a single finite element discretization, to extract the statistics of the interconnect capacitance in an expedient fashion. We demonstrate the accuracy and efficiency of our method through its application to the extraction of capacitances in some representative geometries for IC interconnects

Efficient numerical methods for capacitance extraction based on boundary element method

Fast and accurate solvers for capacitance extraction are needed by the VLSI industry in order to achieve good design quality in feasible time. With the development of technology, this demand is increasing dramatically. Three-dimensional capacitance extraction algorithms are desired due to their high accuracy. However, the present 3D algorithms are slow and thus their application is limited. In this dissertation, we present several novel techniques to significantly speed up capacitance extraction algorithms based on boundary element methods (BEM) and to compute the capacitance extraction in the presence of floating dummy conductors. We propose the PHiCap algorithm, which is based on a hierarchical refinement algorithm and the wavelet transform. Unlike traditional algorithms which result in dense linear systems, PHiCap converts the coefficient matrix in capacitance extraction problems to a sparse linear system. PHiCap solves the sparse linear system iteratively, with much faster convergence, using an efficient preconditioning technique. We also propose a variant of PHiCap in which the capacitances are solved for directly from a very small linear system. This small system is derived from the original large linear system by reordering the wavelet basis functions and computing an approximate LU factorization. We named the algorithm RedCap. To our knowledge, RedCap is the first capacitance extraction algorithm based on BEM that uses a direct method to solve a reduced linear system. In the presence of floating dummy conductors, the equivalent capacitances among regular conductors are required. For floating dummy conductors, the potential is unknown and the total charge is zero. We embed these requirements into the extraction linear system. Thus, the equivalent capacitance matrix is solved directly. The number of system solves needed is equal to the number of regular conductors. Based on a sensitivity analysis, we propose the selective coefficient enhancement method for increasing the accuracy of selected coupling or self-capacitances with only a small increase in the overall computation time. This method is desirable for applications, such as crosstalk and signal integrity analysis, where the coupling capacitances between some conductors needs high accuracy. We also propose the variable order multipole method which enhances the overall accuracy without raising the overall multipole expansion order. Finally, we apply the multigrid method to capacitance extraction to solve the linear system faster. We present experimental results to show that the techniques are significantly more efficient in comparison to existing techniques

The Unified-FFT Method for Fast Solution of Integral Equations as Applied to Shielded-Domain Electromagnetics

Electromagnetic (EM) solvers are widely used within computer-aided design (CAD) to improve and ensure success of circuit designs. Unfortunately, due to the complexity of Maxwell\u27s equations, they are often computationally expensive. While considerable progress has been made in the realm of speed-enhanced EM solvers, these fast solvers generally achieve their results through methods that introduce additional error components by way of geometric approximations, sparse-matrix approximations, multilevel decomposition of interactions, and more. This work introduces the new method, Unified-FFT (UFFT). A derivative of method of moments, UFFT scales as O(N log N), and achieves fast analysis by the unique combination of FFT-enhanced matrix fill operations (MFO) with FFT-enhanced matrix solve operations (MSO). In this work, two versions of UFFT are developed, UFFT-Precorrected (UFFT-P) and UFFT-Grid Totalizing (UFFT-GT). UFFT-P uses precorrected FFT for MSO and allows the use of basis functions that do not conform to a regular grid. UFFT-GT uses conjugate gradient FFT for MSO and features the capability of reducing the error of the solution down to machine precision. The main contribution of UFFT-P is a fast solver, which utilizes FFT for both MFO and MSO. It is demonstrated in this work to not only provide simulation results for large problems considerably faster than state of the art commercial tools, but also to be capable of simulating geometries which are too complex for conventional simulation. In UFFT-P these benefits come at the expense of a minor penalty to accuracy. UFFT-GT contains further contributions as it demonstrates that such a fast solver can be accurate to numerical precision as compared to a full, direct analysis. It is shown to provide even more algorithmic efficiency and faster performance than UFFT-P. UFFT-GT makes an additional contribution in that it is developed not only for planar geometries, but also for the case of multilayered dielectrics and metallization. This functionality is particularly useful for multi-layered printed circuit boards (PCBs) and integrated circuits (ICs). Finally, UFFT-GT contributes a 3D planar solver, which allows for current to be discretized in the z-direction. This allows for similar fast and accurate simulation with the inclusion of some 3D features, such as vias connecting metallization planes

Field solver technologies for variation-aware interconnect parasitic extraction

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 207-213).Advances in integrated circuit manufacturing technologies have enabled high density onchip integration by constantly scaling down the device and interconnect feature size. As a consequence of the ongoing technology scaling (from 45nm to 32nm, 22nm and beyond), geometrical variabilities induced by the uncertainties in the manufacturing processes are becoming more significant. Indeed, the dimensions and shapes of the manufactured devices and interconnect structures may vary by up to 40% from their design intent. The effect of such variabilities on the electrical characteristics of both devices and interconnects must be accurately evaluated and accounted for during the design phase. In the last few years, there have been several attempts to develop variation-aware extraction algorithms, i.e. algorithms that evaluate the effect of geometrical variabilities on the electrical characteristics of devices and interconnects. However, most algorithms remain computationally very expensive. In this thesis the focus is on variation-aware interconnect parasitic extraction. In the first part of the thesis several discretization-based variation-aware solver techniques are developed. The first technique is a stochastic model reduction algorithm (SMOR) The SMOR guarantees that the statistical moments computed from the reduced model are the same as those of the full model. The SMOR works best for problems in which the desired electrical property is contained in an easily defined subspace.(cont.) The second technique is the combined Neumann Hermite expansion (CNHE). The CNHE combines the advantages of both the standard Neumann expansion and the standard stochastic Galerkin method to produce a very efficient extraction algorithm. The CNHE works best in problems for which the desired electrical property (e.g. impedance) is accurately expanded in terms of a low order multivariate Hermite expansion. The third technique is the stochastic dominant singular vectors method (SDSV). The SDSV uses stochastic optimization in order to sequentially determine an optimal reduced subspace, in which the solution can be accurately represented. The SDSV works best for large dimensional problems, since its complexity is almost independent of the size of the parameter space. In the second part of the thesis, several novel discretization-free variation aware extraction techniques for both resistance and capacitance extraction are developed. First we present a variation-aware floating random walk (FRW) to extract the capacitance/resistance in the presence of non-topological (edge-defined) variations. The complexity of such algorithm is almost independent of the number of varying parameters. Then we introduce the Hierarchical FRW to extract the capacitance/resistance of a very large number of topologically different structures, which are all constructed from the same set of building blocks. The complexity of such algorithm is almost independent of the total number of structures. All the proposed techniques are applied to a variety of examples, showing orders of magnitude reduction in the computational time compared to the standard approaches. In addition, we solve very large dimensional examples that are intractable when using standard approaches.by Tarek Ali El-Moselhy.Ph.D

Rapid solution of potential integral equations in complicated 3-dimensional geometries

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (p. 133-137).by Joel Reuben Phillips.Ph.D

Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits

With VLSI(very large scale integration) technology shrinking and frequency increasing, the minimum feature size is smaller than sub-wavelength lithography wavelength, and the manufacturing cost is significantly increasing in order to achieve a good yield. Consequently design companies need to further lower power consumption. All these factors bring new challenges; simulation and modeling need to handle more design constraints, and need to work with modern manufacturing processes. In this dissertation, algorithms and new methodology are presented for these problems: (1) fast and accurate capacitance extraction, (2) capacitance extraction considering lithography effect, (3) BEOL(back end of line) impact on SRAM(static random access memory) performance and yield, and (4) new physical synthesis optimization flow is used to shed area and reduce the power consumption. Interconnect parasitic extraction plays an important role in simulation, verification, optimization. A fast and accurate parasitic extraction algorithm is always important for a current design automation tool. In this dissertation, we propose a new algorithm named HybCap to efficiently handle multiple planar, conformal or embedded dielectric media. From experimental results, the new method is significantly faster than the previous one, 77X speedup, and has a 99% memory savings compared with FastCap and 2X speedup, and has an 80% memory savings compared with PHiCap for complex dielectric media. In order to consider lithography effect in the existing LPE(Layout Parasitic Extraction) flow, a modified LPE flow and fast algorithms for interconnect parasitic extraction are proposed in this dissertation. Our methodology is efficient, compatible with the existing design flow and has high accuracy. With the new enhanced parasitic extraction flow, simulation of BEOL effect on SRAM performance becomes possible. A SRAM simulation model with internal cell interconnect RC parasitics is proposed in order to study the BEOL lithography impact. The impact of BEOL variations on memory designs are systematically evaluated in this dissertation. The results show the power estimation with our SRAM model is more accurate. Finally, a new optimization flow to shed area blow in the design synthesis flow is proposed, which is one level beyond simulation and modeling to directly optimize design, but is also built upon accurate simulations and modeling. Two simple, yet efficient, buffering and gate sizing techniques are presented. On 20 industrial designs in 45nm and 65nm, our new work achieves 12.5% logic area growth reduction, 5.8% total area reduction, 10% wirelength reduction and 770 ps worst slack improvement on average

Efficient numerical algorithms for surface formulations of mathematical models for biomolecule analysis and design

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 179-183).This thesis presents a set of numerical techniques that extend and improve computational modeling approaches for biomolecule analysis and design. The presented research focuses on surface formulations of modeling problems related to the estimation of the energetic cost to transfer a biomolecule from the gas phase to aqueous solution. The thesis discusses four contributions to modeling biomolecular interactions. First, the thesis presents an approach to allow accurate discretization of the most prevalent mathematical definitions of the biomolecule-solvent interface; also presented are a number of accurate techniques for numerically integrating possibly singular functions over the discretized surfaces. Such techniques are essential for solving surface formulations numerically. The second part of the thesis presents a fast multiscale numerical algorithm, FFTSVD, that efficiently solves large boundary-element method problems in biomolecule electrostatics. The algorithm synthesizes elements of other popular fast algorithms to achieve excellent efficiency and flexibility. The third thesis component describes an integral-equation formulation and boundary-element method implementation for biomolecule electrostatic analysis.(cont.) The formulation and implementation allow the solution of complicated molecular topologies and physical models. Furthermore, by applying the methods developed in the first half of the thesis, the implementation can deliver superior accuracy for competitive performance. Finally, the thesis describes a highly efficient numerical method for calculating a biomolecular charge distribution that minimizes the free energy' change of binding to another molecule. The approach, which represents a novel PDE-constrained methodology, builds on well-developed physical theory. Computational results illustrate not only the method's improved performance but also its application to realistic biomolecule problems.by Jaydeep Porter Bardhan.Ph.D

Efficient 3D capacitance extraction solver using instantiable basis functions for VLSI interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 62-65).State-of-the-art capacitance extraction methods for Integrated Circuits (IC) involve scanning 2D cross-sections, and interpolating 2D capacitance values using a table lookup approach. This approach is fast and accurate for a large percentage of IC wires. It is however quite inaccurate for full 3D structures, such as crossing wires in adjacent metal layers. For such cases electrostatic field solvers are required. Unfortunately standard field solvers are inherently very time-consuming, making them completely impractical in typical IC design flows. Even fast matrix-vector product approaches (e.g., fastmultipole or precorrected FFT) are inefficient for these structures since they have a significant computational overhead and scale linearly with the number of conductors only for much larger structures with more than several hundreds of wires. In this talk we present therefore a new 3D extraction field solver that is extremely efficient in particular for the smaller scale extraction problem involving the ten to one hundred conductors in the 3D structures that cannot be handled by the 2D scanning and table look up approach. Because of highly restrictive design rules of the recent sub-micro to nano-scale IC technologies, smooth and regular charge distributions extracted from simple model structures can be stored beforehand as "templates" and instantiated and stretched to fit practical complicated cases as basis function building blocks. This "template-instantiated" strategy largely reduces the number of unknowns and computational time without additional overhead. Given that all basis functions are obtained by the same very few stretched templates, Galerkin coefficients can be readily computed from a mixture of analytical, numerical and table lookup approaches. Furthermore, given the low accuracy (i.e., 3%-5%) required by IC extraction and the specific aspect ratios and separations of wires on ICs, we have observed in our numerical experimentations that edge and corner charge singularities do not need to be included in our templates, hence reducing the complexity of our solver even further.by Yu-Chung Hsiao.S.M