1,209 research outputs found
Kecerdasan matematik-logik dalam kalangan pelajar sarjana Pendidikan Teknik dan Vokasional UTHM
Kecerdasan matematik-logik sering dikaitkan dengan penguasaan pelajar dalam subjek
matematik. Pencapaian pelajar, khususnya pelajar Sarjana Pendidikan Teknik dan
Vokasional, Universiti Tun Hussein Onn Malaysia (UTHM) dalam kursus Statistik dalam
Penyelidikan sedikit sebanyak mempengaruhi pencapaian akademik pelajar. Oleh itu,
kajian ini dijalankan untuk mengkaji pengaruh kecerdasan matematik-logik terhadap
pencapaian pelajar dalam kursus Statistik dalam Penyelidikan. Kajian berbentuk tinjauan
secara kuantitatif untuk melihat hubungan diantara dua pembolehubah iaitu pembolehubah
tidak bersandar (kecerdasan matematik-logik) dan pembolehubah bersandar (penguasaan
pelajar dalam kursus Statistik dalam Penyelidikan). Persampelan rawak mudah digunakan
dalam kajian ini dengan mengambil sampel seramai 108 orang pelajar Sarjana Pendidikan
Teknik dan Vokasional sebagai responden kajian. Data diperoleh daripada sampel dengan
menggunakan borang soal selidik yang diolah berdasarkan alat pengukuran kecerdasan
MIDAS (Multiple Intelligence Development Assessment Scales). Data dianalisis
menggunakan perisian SPSS (Statistical Package for Social Science) versi 16.0 yang
melibatkan ujian statistik skor min dan kolerasi pangkat Spearman. Hasil dapatan kajian
menunjukkan tahap kecenderungan kecerdasan matematik-logik pelajar berada pada tahap
yang tinggi dan mempunyai hubungan yang signifikan dengan pencapaian pelajar dalam
kursus Statistik dalam Penyelidikan. Berdasarkan dapatan kajian boleh disimpulkan
bahawa kecerdasan matematik-logik dapat dijadikan kayu ukur dalam memastikan
kejayaan pelajar
The s-mote: a versatile heterogeneous multi-radio platform for wireless sensor networks applications
This paper presents a novel architecture and its
implementation for a versatile, miniaturised mote which
can communicate concurrently using a variety of
combinations of ISM bands, has increased processing
capability, and interoperability with mainstream GSM
technology. All these features are integrated in a small
form factor platform. The platform can have many
configurations which could satisfy a variety of
applications’ constraints. To the best of our knowledge, it
is the first integrated platform of this type reported in the literature. The proposed platform opens the way for
enhanced levels of Quality of Service (QoS), with respect to
reliability, availability and latency, in addition to
facilitating interoperability and power reduction
compared to existing platforms. The small form factor also
allows potential of integration with other mobile platforms
including smart phones
Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals
Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve
RF-Transformer: A Unified Backscatter Radio Hardware Abstraction
This paper presents RF-Transformer, a unified backscatter radio hardware
abstraction that allows a low-power IoT device to directly communicate with
heterogeneous wireless receivers at the minimum power consumption. Unlike
existing backscatter systems that are tailored to a specific wireless
communication protocol, RF-Transformer provides a programmable interface to the
micro-controller, allowing IoT devices to synthesize different types of
protocol-compliant backscatter signals sharing radically different PHY-layer
designs. To show the efficacy of our design, we implement a PCB prototype of
RF-Transformer on 2.4 GHz ISM band and showcase its capability on generating
standard ZigBee, Bluetooth, LoRa, and Wi-Fi 802.11b/g/n/ac packets. Our
extensive field studies show that RF-Transformer achieves 23.8 Mbps, 247.1
Kbps, 986.5 Kbps, and 27.3 Kbps throughput when generating standard Wi-Fi,
ZigBee, Bluetooth, and LoRa signals while consuming 7.6-74.2 less power than
their active counterparts. Our ASIC simulation based on the 65-nm CMOS process
shows that the power gain of RF-Transformer can further grow to 92-678. We
further integrate RF-Transformer with pressure sensors and present a case study
on detecting foot traffic density in hallways. Our 7-day case studies
demonstrate RFTransformer can reliably transmit sensor data to a commodity
gateway by synthesizing LoRa packets on top of Wi-Fi signals. Our experimental
results also verify the compatibility of RF-Transformer with commodity
receivers. Code and hardware schematics can be found at:
https://github.com/LeFsCC/RF-Transformer
A Comprehensive Analysis of Literature Reported Mac and Phy Enhancements of Zigbee and its Alliances
Wireless communication is one of the most required technologies by the common man. The strength of this technology is rigorously progressing towards several novel directions in establishing personal wireless networks mounted over on low power consuming systems. The cutting-edge communication technologies like bluetooth, WIFI and ZigBee significantly play a prime role to cater the basic needs of any individual. ZigBee is one such evolutionary technology steadily getting its popularity in establishing personal wireless networks which is built on small and low-power digital radios. Zigbee defines the physical and MAC layers built on IEEE standard. This paper presents a comprehensive survey of literature reported MAC and PHY enhancements of ZigBee and its contemporary technologies with respect to performance, power consumption, scheduling, resource management and timing and address binding. The work also discusses on the areas of ZigBee MAC and PHY towards their design for specific applications
FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review
The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the well-known AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management
Capsule endoscopy system with novel imaging algorithms
Wireless capsule endoscopy (WCE) is a state-of-the-art technology to receive images of human intestine for medical diagnostics. In WCE, the patient ingests a specially designed electronic capsule which has imaging and wireless transmission capabilities inside it. While the capsule travels through the gastrointestinal (GI) tract, it captures images and sends them wirelessly to an outside data logger unit. The data logger stores the image data and then they are transferred to a personal computer (PC) where the images are reconstructed and displayed for diagnosis. The key design challenge in WCE is to reduce the area and power consumption of the capsule while maintaining acceptable image reconstruction.
In this research, the unique properties of WCE images are identified by analyzing hundreds of endoscopic images and video frames, and then these properties are used to develop novel and low complexity compression algorithms tailored for capsule endoscopy. The proposed image compressor consists of a new YEF color space converter, lossless prediction coder, customizable chrominance sub-sampler and an efficient Golomb-Rice encoder. The scheme has both lossy and lossless modes and is further customized to work with two lighting modes – conventional white light imaging (WLI) and emerging narrow band imaging (NBI). The average compression ratio achieved using the proposed lossy compression algorithm is 80.4% for WBI and 79.2% for NBI with high reconstruction quality index for both bands. Two surveys have been conducted which show that the reconstructed images have high acceptability among medical imaging doctors and gastroenterologists.
The imaging algorithms have been realized in hardware description language (HDL) and their functionalities have been verified in field programmable gate array (FPGA) board. Later it was implemented in a 0.18 μm complementary metal oxide semiconductor (CMOS) technology and the chip was fabricated. Due to the low complexity of the core compressor, it consumes only 43 µW of power and 0.032 mm2 of area. The compressor is designed to work with commercial low-power image sensor that outputs image pixels in raster scan fashion, eliminating the need of significant input buffer memory.
To demonstrate the advantage, a prototype of the complete WCE system including an FPGA based electronic capsule, a microcontroller based data logger unit and a Windows based image reconstruction software have been developed. The capsule contains the proposed low complexity image compressor and can generate both lossy and lossless compressed bit-stream. The capsule prototype also supports both white light imaging (WLI) and narrow band imaging (NBI) imaging modes and communicates with the data logger in full duplex fashion, which enables configuring the image size and imaging mode in real time during the examination. The developed data logger is portable and has a high data rate wireless connectivity including Bluetooth, graphical display for real time image viewing with state-of-the-art touch screen technology. The data are logged in micro SD cards and can be transferred to PC or Smartphone using card reader, USB interface, or Bluetooth wireless link. The workstation software can decompress and show the reconstructed images. The images can be navigated, marked, zoomed and can be played as video. Finally, ex-vivo testing of the WCE system has been done in pig's intestine to validate its performance
- …