The Design and Linearization of 60GHz Injection Locked Power Amplifier

The RF power amplifier is one of the most critical blocks of transceivers, as it is expected to provide a suitable output power with high gain, efficiency and linearity. In this paper, a 60-GHz power amplifier based on an injection locked structure is demonstrated in a standard 65 CMOS technology. The PA core consists of a cross-coupled pair of NMOS transistors with an NMOS current source. This structure can achieve large output power and high PAE, but with poor linearity performance. In order to improve the linearity, several linearization techniques are investigated, including adaptive biasing and predistortion. The results show that the adaptive biasing technique can enlarge the linear operation region, but results in poor AM-PM performance. By instead using the predistortion technique, the AM-PM performance can be improved, but the linear region only extends slightly. Considering theses two techniques different advantages, we combine them together to improve not only the linear region but also the AM-PM performance. Finally, a common source amplifier is added as the first stage. With proper bias, the linear operation region is then effectively extended by 7.3 dB. This two stage power amplifier achieves large output power, high linearity and high PAE simultaneously. It delivers a gain of 20dB, a Psat of 16.3dBm, a P1dB of 15.41dBm, and a PAE of 30%.Since the invention of radio-frequency (RF) wireless communication more than 100 years ago, mobile phones and other wireless communications products for civilian consumption have developed rapidly. Nowadays, the demand for larger high data rate and capacities is rising sharply. The traditional wireless bandwidth is no longer able to meet some high-rate applications requirement. However, 60GHz wireless communication system is our solution, and up to 7 GHz unlicensed wide band around 60GHz is open to use across much of the world. Furthermore, the power amplifier (PA) is a critical part of any transmitter to convert the signal to higher power and drive the antenna. For power amplifiers, efficiency and linearity are most important. Power amplifiers with low efficiency will result in high level of heat dissipation. Linearity is a measure of the signal distortion, which consists of gain compression (AM-AM distortion) and phase distortion (AM-PM distortion). In this thesis work, an injection locked power amplifier is used to reduce the input driving requirements and improve the efficiency. Simulations have been performed for implementation in 65nm standard CMOS, which is a low-cost technology for fabrication of integrated circuits (chips). The injection locked technique means that a self-oscillating circuit is forced to run at the same frequency as the input signal. Furthermore, an integrated balun is added to transfer between single-ended and differential signals. The results show that this PA can achieve high efficiency but with poor linearity performance. In order to improve the linearity, different linearization techniques are investigated, including adaptive biasing and predistortion. Adaptive biasing is a feedback technique. At high output levels, the power amplifier has less gain, which leads to signal distortion. The adaptive biasing unit can sense the output power in real time and adjust the bias. The bias is then increased at increased output power in order to restore the power gain at high output levels. Predistortion is another linearization technique. A predistorter, which has a gain expansion characteristic, is then introduced before the PA to compensate for its gain reduction. Then, considering the advantages of these two linearization techniques, we combine them together to achieve even better results. Finally, a two-stage power amplifier is proposed by adding a common source amplifier as the first stage. The first stage can also produce a gain boost at the high output levels, and this expansion gain can be made to match the second-stage gain reduction very well. The simulation results show that the amplifier can achieve high linearity and efficiency at the same time

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

A linear high-efficiency millimeter-wave CMOS Doherty radiator leveraging on-antenna active load-modulation

This thesis presents a Doherty Radiator architecture that explores multi-feed antennas to achieve an on-antenna Doherty load modulation network and demonstrate high-speed high-efficiency transmission of wideband modulated signals. On the passive circuits, we exploit the multi-feed antenna concept to realize compact and high-efficiency on-antenna active load modulation for close-to-ideal Doherty operation, on-antenna power combining, and mm-Wave signal radiation. Moreover, we analyze the far-field transmission of the proposed Doherty Radiator and demonstrate its wide Field-of-View (FoV). On the active circuits, we employ a GHz-bandwidth adaptive biasing at the Doherty Auxiliary power amplifier (PA) path to enhance the Main/Auxiliary Doherty cooperation and appropriate turning-on/-off of the Auxiliary path. A proof-of-concept Doherty Radiator implemented in a 45nm CMOS SOI process over 62-68GHz exhibits a consistent 1.45-1.53× PAE enhancement at 6dB PBO over an idealistic class-B PA with the same PAE at P1dB. The measured Continuous-Wave (CW) performance at 65GHz demonstrates 19.4/19.2dBm PSAT/P1dB and achieves 27.5%/20.1% PAE at peak/6dB PBO, respectively. For single-carrier 1Gsym/s 64-QAM modulation, the Doherty Radiator shows average output power of 14.2dBm with an average 20.2% PAE and -26.7dB EVM without digital predistortion. Consistent EVMs are observed over the entire antenna FoV, demonstrating spatially undistorted transmission and constant Doherty PBO efficiency enhancement.M.S

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

Millimetre-Wave Fibre-Wireless Technologies for 5G Mobile Fronthaul

The unprecedented growth in mobile data traffic, driven primarily by bandwidth rich applications and high definition video is accelerating the development of fifth generation (5G) mobile network. As mobile access network evolves towards centralisation, mobile fronthaul (MFH) architecture becomes essential in providing high capacity, ubiquitous and yet affordable services to subscribers. In order to meet the demand for high data rates in the access, Millimetre-wave (mmWave) has been highlighted as an essential technology in the development of 5G-new radio (5G-NR). In the present MFH architecture which is typically based on common public radio interface (CPRI) protocol, baseband signals are digitised before fibre transmission, featuring high overhead data and stringent synchronisation requirements. A direct application of mmWave 5G-NR to CPRI digital MFH, where signal bandwidth is expected to be up to 1GHz will be challenging, due to the increased complexity of the digitising interface and huge overhead data that will be required for such bandwidth. Alternatively, radio over fibre (RoF) technique can be employed in the transportation of mmWave wireless signals via the MFH link, thereby avoiding the expensive digitisation interface and excessive overhead associated with its implementation. Additionally, mmWave carrier can be realised with the aid of photonic components employed in the RoF link, further reducing the system complexity. However, noise and nonlinearities inherent to analog transmission presents implementation challenges, limiting the system dynamic range. Therefore, it is important to investigate the effects of these impairments in RoF based MFH architecture. This thesis presents extensive research on the impact of noise and nonlinearities on 5G candidate waveforms, in mmWave 5G fibre wireless MFH. Besides orthogonal frequency division multiplexing (OFDM), another radio access technology (RAT) that has received significant attention is filter bank multicarrier (FBMC), particularly due to its high spectral containment and excellent performance in asynchronous transmission. Hence, FBMC waveform is adopted in this work to study the impact of noise and nonlinearities on the mmWave fibre-wireless MFH architecture. Since OFDM is widely deployed and it has been adopted for 5G-NR, the performance of OFDM and FBMC based 5G mmWave RAT in fibre wireless MFH architecture is compared for several implementations and transmission scenarios. To this extent, an end to end transmission testbed is designed and implemented using industry standard VPI Transmission Maker® to investigate five mmWave upconversion techniques. Simulation results show that the impact of noise is higher in FBMC when the signal to-noise (SNR) is low, however, FBMC exhibits better performance compared to OFDM as the SNR improved. More importantly, an evaluation of the contribution of each noise component to the overall system SNR is carried out. It is observed in the investigation that noise contribution from the optical carriers employed in the heterodyne upconversion of intermediate frequency (IF) signals to mmWave frequency dominate the system noise. An adaptive modulation technique is employed to optimise the system throughput based on the received SNR. The throughput of FBMC based system reduced significantly compared to OFDM, due to laser phase noise and chromatic dispersion (CD). Additionally, it is shown that by employing frequency domain averaging technique to enhance the channel estimation (CE), the throughput of FBMC is significantly increased and consequently, a comparable performance is obtained for both waveforms. Furthermore, several coexistence scenarios for multi service transmission are studied, considering OFDM and FBMC based RATs to evaluate the impact inter band interference (IBI), due to power amplifier (PA) nonlinearity on the system performance. The low out of band (OOB) emission in FBMC plays an important role in minimising IBI to adjacent services. Therefore, FBMC requires less guardband in coexistence with multiple services in 5G fibre-wireless MFH. Conversely, OFDM introduced significant OOB to adjacent services requiring large guardband in multi-service coexistence transmission scenario. Finally, a novel transmission scheme is proposed and investigated to simultaneously generate multiple mmWave signals using laser heterodyning mmWave upconversion technique. With appropriate IF and optical frequency plan, several mmWave signals can be realised. Simulation results demonstrate successful simultaneous realisation of 28GHz, 38GHz, and 60GHz mmWave signals

Millimetre Wave Series Connected Doherty PA Using 45nm SOI Process

With the high demand for high data rate communication systems, it is expected that wireless networks will migrate into the unexploited millimeter-wave frequencies. This migration and the utilization of wide-band digitally modulated signal possessing of high Peak-to-Average-Power- Ratio (PAPR) brings diffcult challenges in attaining a satisfactory trade-off between linearity and efficiency when designing mm-wave power amplifiers (PAs). There are various methods of maximizing the output power and peak effciency of mm-wave PAs that use deep-sub-micron technologies. Of these methods, little attention has been given to the efficiency enhancement of PAs in back-off region. The use of the Doherty technique in the mm-wave frequencies has attracted little attention. This is mainly due to complexity in realizing the quarter-wave impedance inverter and the low-gain of the class-C operating peaking transistor using deep-sub-micron technologies. In this thesis, a series-connected-load (SCL) Doherty topology is proposed to enhance the efficiency of a millimeter-wave power amplifier realized on a deep-sub-micron semiconductor technology. The output combiner is determined by the ABCD matrices of the ideal combiner network in the SCL Doherty PA to ensure proper load modulation. Then, it describes the methodology applied to realize the transformer-based combiner networks while absorbing the parasitic capacitance of the transistors to maximize efficiency in the back-off region. This methodology is then applied to realize a two-stage SCL Doherty PA in 45 nm Silicon-on- Insulator CMOS technology to operate at 60 GHz

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

A 40-GHz Load Modulated Balanced Power Amplifier using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS

© 2023 IEEE - All rights reserved. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSI.2023.3282731 ​​​​​​​In this work, a ten-way power-combined poweramplifier is designed using a load modulated balanced amplifier(LMBA)-based architecture. To provide the required magnitudeand phase controls between the main and control-signal paths ofthe LMBA, an unequal power splitter and a phase compensationnetwork are proposed. As proof of concept, the designed poweramplifier is implemented in a 45-nm SOI CMOS process. At 40GHz, it delivers a 25.1 dBm Psat with a peak power-addedefficiency (PAE) of 27.9%. At 6-dB power back-off level, itachieves 1.39 times drain efficiency enhancement over an idealClass-B power amplifier. Using a 200-MHz single-carrier 64-QAMsignal, the designed amplifier delivers an average output power of16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB andACPR of -25.3 dBc. The die size, including all testing pads, is only1.92 mm2. To the best of the authors’ knowledge, compared withthe other recently published silicon-based LMBAs, this designachieves the highest Psat.Peer reviewe

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day