Dynamic Polymorphic Reconfiguration to Effectively “CLOAK” a Circuit’s Function

Today\u27s society has become more dependent on the integrity and protection of digital information used in daily transactions resulting in an ever increasing need for information security. Additionally, the need for faster and more secure cryptographic algorithms to provide this information security has become paramount. Hardware implementations of cryptographic algorithms provide the necessary increase in throughput, but at a cost of leaking critical information. Side Channel Analysis (SCA) attacks allow an attacker to exploit the regular and predictable power signatures leaked by cryptographic functions used in algorithms such as RSA. In this research the focus on a means to counteract this vulnerability by creating a Critically Low Observable Anti-Tamper Keeping Circuit (CLOAK) capable of continuously changing the way it functions in both power and timing. This research has determined that a polymorphic circuit design capable of varying circuit power consumption and timing can protect a cryptographic device from an Electromagnetic Analysis (EMA) attacks. In essence, we are effectively CLOAKing the circuit functions from an attacker

Effects of Architecture on Information Leakage of a Hardware Advanced Encryption Standard Implementation

Side-channel analysis (SCA) is a threat to many modern cryptosystems. Many countermeasures exist, but are costly to implement and still do not provide complete protection against SCA. A plausible alternative is to design the cryptosystem using architectures that are known to leak little information about the cryptosystem\u27s operations. This research uses several common primitive architectures for the Advanced Encryption Standard (AES) and assesses the susceptibility of the full AES system to side-channel attack for various primitive configurations. A combined encryption/decryption core is also evaluated to determine if variation of high-level architectures affects leakage characteristics. These different configurations are evaluated under multiple measurement types and leakage models. The results show that different hardware configurations do impact the amount of information leaked by a device, but none of the tested configurations are able to prevent exploitation

Diseño y caracterización de criptocircuitos seguros y resistentes a ataques físicos.

A diario personas de todo el mundo hacen uso de dispositivos electrónicos en los que almacenan o con los que intercambian información privada. La confidencialidad y privacidad es un derecho frente a posibles intrusos, por lo que la seguridad en las nuevas tecnologías es un factor de transcendental importancia que exige la atención de la comunidad científica. Los dispositivos electrónicos considerados “seguros”, de facto cualquier dispositivo electrónico de uso en telecomunicaciones o que maneje información relevante, hacen uso de la criptografía para garantizar la confidencialidad, autenticación e integridad de los datos procesados. Estos dispositivos criptográficos implementan algoritmos matemáticamente seguros, pero que, debido a su implementación física, pueden revelar información sensible por las fugas de información durante su operación, que pueden ser aprovechadas por un atacante para revelar la clave secreta del dispositivo. Estos ataques, conocidos como ataques de canal lateral, o simplemente ataques laterales, son muy efectivos y explotan información como puede ser el consumo de potencia, emisión electromagnética o tiempos de ejecución, entre otros, para revelar la clave secreta. La comunidad científica ha centrado su esfuerzo en el diseño de contramedidas para evitar este tipo de ataques. El objetivo principal de esta Tesis es aumentar la seguridad de dispositivos criptográficos hardware frente ataques laterales. Para conseguir este objetivo se han realizado las 3 siguientes macro tareas: 1. Medidas de vulnerabilidad de un dispositivo criptográfico (realización de ataques y métricas de seguridad). 2. Propuestas de contramedidas. 3. Evaluación de su seguridad. Para la medida de vulnerabilidad de los dispositivos criptográficos, se han implementado tanto ataques basados en el consumo de potencia, como ataques electromagnéticos o el uso de otras métricas como por ejemplo el t-test. Para probar la efectividad de los ataques, se han realizado sobre sistemas de clave privada, utilizándose como demostradores cifradores de bloque (AES y una parte del algoritmo KASUMI) y cifradores de flujo (Trivium). Estas medidas se han realizado tanto en entornos de simulación como de forma experimental, sobre implementaciones ASIC o FPGA. Además, se han evaluado diferentes métricas y test alternativos para poder evaluar la seguridad en diferentes etapas de diseño, así como el poder determinar el nivel de seguridad sin tener que llevar a cabo un ataque completo. Por otra parte, se han propuesto diferentes metodologías de diseño de contramedidas frente ataques laterales aplicadas a diferentes niveles de abstracción. Las propuestas a nivel de transistor consisten en modificar las estructuras de las celdas lógicas diseñadas para poder obtener un consumo de potencia igual independientemente del dato procesado. A nivel de puerta se proponen diferentes técnicas que varían la temporización del circuito, modificando así los niveles de seguridad alcanzados por los criptocircuitos diseñados. Estas contramedidas, son complementarias y por tanto ambas aplicables en un mismo diseño. Finalmente, cumplidas las dos tareas anteriores, se ha pasado a una etapa de diseño donde se han integrado en un ASIC los casos de estudio que implementan bloques criptográficos aplicando las contramedidas propuestas a lo largo del desarrollo de la Tesis. La caracterización de los diferentes casos de estudio determinará de forma experimental la ganancia en seguridad obtenida por cada contramedida.Every day, people all over the world use electronic devices to store or exchange private information with each other. Confidentiality and privacy is a right against possible intruders, so security in new technologies is an important factor that requires the attention of the scientific community. Electronic devices considered "secure", in fact any electronic device for use in telecommunications or handling relevant information, make use of cryptography to ensure the confidentiality, authentication and integrity of the data processed. These cryptographic devices implement mathematically secure algorithms, but due to their physical implementation, they can reveal sensitive information due to data leaks during their normal operation, which can be exploited by an attacker to reveal the device’s secret key. These attacks, known as side channel attacks, are very effective and exploit information such as power consumption, electromagnetic radiation or timing, among others, to reveal the secret key. The scientific community has focused its efforts on the design of countermeasures to prevent this type of attack. The main objective of this Thesis is to increase the security of hardware cryptographic devices against side channel attacks. To achieve this objective, the following 3 tasks have been carried out: 1. Vulnerability measurements of a cryptographic device (execution of attacks and security metrics). 2. Proposals for countermeasures. 3. Security assessment. To measure the vulnerability of cryptographic devices, attacks based on power consumption, electromagnetic attacks or the use of other metrics such as t-test have been implemented. To test the effectiveness of the attacks, they have been performed on private key systems, using block cipher demonstrators (AES and a part of the KASUMI algorithm) and stream ciphers (Trivium). These measurements have been carried out both in simulation environments and experimentally on ASIC or FPGA implementations. In addition, different alternative metrics and tests have been evaluated in order to evaluate security at different stages of design, as well as to determine the level of security without having to carry out a complete attack. On the other hand, different methodologies have been proposed for the design of countermeasures against side channel attacks applied at different levels of abstraction. The proposals at the transistor level consist of modifying the structures of the designed logic cells to obtain an equal power consumption independently of the processed data. At the gate level, different techniques are proposed that vary the timing of the circuit, thus modifying the security levels achieved by the designed cryptocircuits. These countermeasures are complementary and therefore both applicable in the same design. Finally, once the two previous tasks had been completed, a design stage has been undertaken where the case studies implementing cryptographic blocks have been integrated into an ASIC, applying the countermeasures proposed throughout the development of the Thesis. The characterization of the different case studies will experimentally determine the security gain obtained by each countermeasure

Exploitation of Unintentional Information Leakage from Integrated Circuits

Unintentional electromagnetic emissions are used to recognize or verify the identity of a unique integrated circuit (IC) based on fabrication process-induced variations in a manner analogous to biometric human identification. The effectiveness of the technique is demonstrated through an extensive empirical study, with results presented indicating correct device identification success rates of greater than 99:5%, and average verification equal error rates (EERs) of less than 0:05% for 40 near-identical devices. The proposed approach is suitable for security applications involving commodity commercial ICs, with substantial cost and scalability advantages over existing approaches. A systematic leakage mapping methodology is also proposed to comprehensively assess the information leakage of arbitrary block cipher implementations, and to quantitatively bound an arbitrary implementation\u27s resistance to the general class of differential side channel analysis techniques. The framework is demonstrated using the well-known Hamming Weight and Hamming Distance leakage models, and approach\u27s effectiveness is demonstrated through the empirical assessment of two typical unprotected implementations of the Advanced Encryption Standard. The assessment results are empirically validated against correlation-based differential power and electromagnetic analysis attacks

Side-channel attacks and countermeasures in the design of secure IC's devices for cryptographic applications

Abstract--- A lot of devices which are daily used have to guarantee the retention of sensible data. Sensible data are ciphered by a secure key by which only the key holder can get the data. For this reason, to protect the cipher key against possible attacks becomes a main issue. The research activities in hardware cryptography are involved in finding new countermeasures against various attack scenarios and, in the same time, in studying new attack methodologies. During the PhD, three different logic families to counteract Power Analysis were presented and a novel class of attacks was studied. Moreover, two different activities related to Random Numbers Generators have been addressed

Enhancing Electromagnetic Side-Channel Analysis in an Operational Environment

Side-channel attacks exploit the unintentional emissions from cryptographic devices to determine the secret encryption key. This research identifies methods to make attacks demonstrated in an academic environment more operationally relevant. Algebraic cryptanalysis is used to reconcile redundant information extracted from side-channel attacks on the AES key schedule. A novel thresholding technique is used to select key byte guesses for a satisfiability solver resulting in a 97.5% success rate despite failing for 100% of attacks using standard methods. Two techniques are developed to compensate for differences in emissions from training and test devices dramatically improving the effectiveness of cross device template attacks. Mean and variance normalization improves same part number attack success rates from 65.1% to 100%, and increases the number of locations an attack can be performed by 226%. When normalization is combined with a novel technique to identify and filter signals in collected traces not related to the encryption operation, the number of traces required to perform a successful attack is reduced by 85.8% on average. Finally, software-defined radios are shown to be an effective low-cost method for collecting side-channel emissions in real-time, eliminating the need to modify or profile the target encryption device to gain precise timing information

A Network-based Asynchronous Architecture for Cryptographic Devices

Institute for Computing Systems ArchitectureThe traditional model of cryptography examines the security of the cipher as a mathematical function. However, ciphers that are secure when specified as mathematical functions are not necessarily secure in real-world implementations. The physical implementations of ciphers can be extremely difficult to control and often leak socalled side-channel information. Side-channel cryptanalysis attacks have shown to be especially effective as a practical means for attacking implementations of cryptographic algorithms on simple hardware platforms, such as smart-cards. Adversaries can obtain sensitive information from side-channels, such as the timing of operations, power consumption and electromagnetic emissions. Some of the attack techniques require surprisingly little side-channel information to break some of the best known ciphers. In constrained devices, such as smart-cards, straightforward implementations of cryptographic algorithms can be broken with minimal work. Preventing these attacks has become an active and a challenging area of research. Power analysis is a successful cryptanalytic technique that extracts secret information from cryptographic devices by analysing the power consumed during their operation. A particularly dangerous class of power analysis, differential power analysis (DPA), relies on the correlation of power consumption measurements. It has been proposed that adding non-determinism to the execution of the cryptographic device would reduce the danger of these attacks. It has also been demonstrated that asynchronous logic has advantages for security-sensitive applications. This thesis investigates the security and performance advantages of using a network-based asynchronous architecture, in which the functional units of the datapath form a network. Non-deterministic execution is achieved by exploiting concurrent execution of instructions both with and without data-dependencies; and by forwarding register values between instructions with data-dependencies using randomised routing over the network. The executions of cryptographic algorithms on different architectural configurations are simulated, and the obtained power traces are subjected to DPA attacks. The results show that the proposed architecture introduces a level of non-determinism in the execution that significantly raises the threshold for DPA attacks to succeed. In addition, the performance analysis shows that the improved security does not degrade performance

High-level services for networks-on-chip

Future technology trends envision that next-generation Multiprocessors Systems-on- Chip (MPSoCs) will be composed of a combination of a large number of processing and storage elements interconnected by complex communication architectures. Communication and interconnection between these basic blocks play a role of crucial importance when the number of these elements increases. Enabling reliable communication channels between cores becomes therefore a challenge for system designers. Networks-on-Chip (NoCs) appeared as a strategy for connecting and managing the communication between several design elements and IP blocks, as required in complex Systems-on-Chip (SoCs). The topic can be considered as a multidisciplinary synthesis of multiprocessing, parallel computing, networking, and on- chip communication domains. Networks-on-Chip, in addition to standard communication services, can be employed for providing support for the implementation of system-level services. This dissertation will demonstrate how high-level services can be added to an MPSoC platform by embedding appropriate hardware/software support in the network interfaces (NIs) of the NoC. In this dissertation, the implementation of innovative modules acting in parallel with protocol translation and data transmission in NIs is proposed and evaluated. The modules can support the execution of the high-level services in the NoC at a relatively low cost in terms of area and energy consumption. Three types of services will be addressed and discussed: security, monitoring, and fault tolerance. With respect to the security aspect, this dissertation will discuss the implementation of an innovative data protection mechanism for detecting and preventing illegal accesses to protected memory blocks and/or memory mapped peripherals. The second aspect will be addressed by proposing the implementation of a monitoring system based on programmable multipurpose monitoring probes aimed at detecting NoC internal events and run-time characteristics. As last topic, new architectural solutions for the design of fault tolerant network interfaces will be presented and discussed