On-chip Electro-static Discharge (esd) Protection For Radio-frequency Integrated Circuits

Electrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device\u27s performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD current and limit the overstress voltage under different ESD events. Some effective ESD protection devices were reported for low speed circuit applications such as analog ICs or digital ICs in CMOS process. On the contrast, only a few ESD protection devices available for radio frequency integrated circuits (RF ICs). ESD protection for RF ICs is more challenging than traditional low speed CMOS ESD protection design because of the facts that: (1) Process limitation: High-performance RF ICs are typically fabricated in compound semiconductor process such as GaAs pHEMT and SiGe HBT process. And some proved effective ESD devices (e.g. SCR) are not able to be fabricated in those processes due to process limitation. Moreover, compound semiconductor process has lower thermal conductivity which will worsen its ESD damage immunity. (2) Parasitic capacitance limitation: Even for RF CMOS process, the inherent parasitic capacitance of ESD protection devices is a big concern. Therefore, this dissertation will contribute on ESD protection designs for RF ICs in all the major processes including GaAs pHEMT, SiGe BiCMOS and standard CMOS. iv The ESD protection for RF ICs in GaAs pHEMT process is very difficult, and the typical HBM protection level is below 1-kV HBM level. The first part of our work is to analyze pHEMT\u27s snapback, post-snapback saturation and thermal failure under ESD stress using TLP-like Sentaurus TCAD simulation. The snapback is caused by virtual bipolar transistor due to large electron-hole pairs impacted near drain region. Postsnapback saturation is caused by temperature-induced mobility degradation due to IIIV compound semiconductor materials\u27 poor thermal conductivity. And thermal failure is found to be caused by hot spot located in pHEMT\u27s InGaAs layer. Understanding of these physical mechanisms is critical to design effective ESD protection device in GaAs pHEMT process. Several novel ESD protection devices were designed in 0.5um GaAs pHEMT process. The multi-gate pHEMT based ESD protection devices in both enhancementmode and depletion-mode were reported and characterized then. Due to the multiple current paths available in the multi-gate pHEMT, the new ESD protection clamp showed significantly improved ESD performances over the conventional single-gate pHEMT ESD clamp, including higher current discharge capability, lower on-state resistance, and smaller voltage transient. We proposed another further enhanced ESD protection clamp based on a novel drain-less, multi-gate pHEMT in a 0.5um GaAs pHEMT technology. Based on Barth 4002 TLP measurement results, the ESD protection devices proposed in this chapter can improve the ESD level from 1-kV (0.6 A It2) to up to 8-kV ( \u3e 5.2 A It2) under HBM. v Then we optimized SiGe-based silicon controlled rectifiers (SiGe SCR) in SiGe BiCMOS process. SiGe SCR is considered a good candidate ESD protection device in this process. But the possible slow turn-on issue under CDM ESD events is the major concern. In order to optimize the turn-on performance of SiGe SCR against CDM ESD, the Barth 4012 very fast TLP (vfTLP) and vfTLP-like TCAD simulation were used for characterization and analysis. It was demonstrated that a SiGe SCR implemented with a P PLUG layer and minimal PNP base width can supply the smallest peak voltage and fastest response time which is resulted from the fact that the impact ionization region and effective base width in the SiGe SCR were reduced due to the presence of the P PLUG layer. This work demonstrated a practical approach for designing optimum ESD protection solutions for the low-voltage/radio frequency integrated circuits in SiGe BiCMOS process. In the end, we optimized SCRs in standard silicon-based CMOS process to supply protection for high speed/radio-frequency ICs. SCR is again considered the best for its excellent current handling ability. But the parasitic capacitance of SCRs needs to be reduced to limit SCR\u27s impact to RF performance. We proposed a novel SCR-based ESD structure and characterize it experimentally for the design of effective ESD protection in high-frequency CMOS based integrated circuits. The proposed SCR-based ESD protection device showed a much lower parasitic capacitance and better ESD performance than the conventional SCR and a low-capacitance SCR reported in the literature. The physics underlying the low capacitance was explained by measurements using HP 4284 capacitance meter. vi Throughout the dissertation work, all the measurements are mainly conducted using Barth 4002 transimission line pulsing (TLP) and Barth 4012 very fast transmission line pulsing (vfTLP) testers. All the simulation was performed using Sentaurus TCAD tool from Synopsys

Electrostatic discharge protection circuit for high-speed mixed-signal circuits

ESD, the discharge of electrostatically generated charges into an IC, is one of the most important reliability problems for ultra-scaled devices. This electrostatic charge can generate voltages of up to tens of kilovolts. These very high voltages can generate very high electric fields and currents across semiconductor devices, which may result in dielectric damage or melting of semiconductors and contacts. It has been reported that up to 70% of IC failures are caused by ESD. Therefore, it’s necessary to design a protection circuit for each pin that discharges the ESD energy to the ground. As the devices are continuously scaling down, while ESD energy remains the same, they become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Providing a complete ESD immunity for any circuit involves the design of proper protection circuits for I/O pins in addition to an ESD clamp between power supply pins. In this research both of these aspects are investigated and optimized solutions for them are reported. As Silicon Controlled Rectifier (SCR) has the highest ESD protection level per unit area, ESD protection for I/O pins is provided by optimizing the first breakdown voltage and latch-up immunity of SCR family devices. The triggering voltage of SCR is reduced by a new implementation of gate-substrate triggering technique. Furthermore, a new device based on SCR with internal darlington pair is introduced that can provide ESD protection with very small parasitic capacitance. Besides reducing triggering voltage, latch-up immunity of SCR devices is improved using two novel techniques to increase the holding voltage and the holding current. ESD protection between power rails is provided with transient clamps in which the triggering circuit keeps the clamp “on” during the ESD event. In this research, two new clamps are reported that enhance the triggering circuit of the clamp. The first method uses a CMOS thyristor element to provide enough delay time while the second method uses a flip flop to latch the clamp into “on” state at the ESD event. Moreover, the stability of transient clamps is analyzed and it’s been shown that the two proposed clamps have the highest stability compared to other state of the art ESD clamps. Finally, in order to investigate the impact of ESD protection circuits on high speed applications a current mode logic (CML) driver is designed in 0.13μm CMOS technology. The protection for this driver is provided using both MOS-based and SCR-based protection methods. Measurement results show that, compared to MOS-based protection, SCR-based protection has less impact on the driver performance due to its lower parasitic capacitance

Design, Characterization and Analysis of Component Level Electrostatic Discharge (ESD) Protection Solutions

Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit\u27s operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level. Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC\u27s pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products. Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to ± 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR. Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology. ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices\u27 performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range

Chip- and System-Level Reliability on SiC-based Power Modules

The blocking voltage, switching frequency and temperature tolerance of power devices have been greatly improved due to the revolution of wide bandgap (WBG) materials, such as silicon carbide (SiC) and gallium nitride (GaN). Owing to the development of SiC-based power devices, the power rating, operating voltage, and power density of power modules have been significantly improved. However, the reliability of SiC-based power modules has not been fully explored yet. Thus, this dissertation focuses on the chip- and system-level reliability on SiC-based power modules. For chip-level reliability, this work focuses on on-chip SiC ESD protection devices for SiC-based integrated circuits (ICs). In order to develop SiC ESD protection devices, SiC-based Ohmic contact and ion implantation have been studied. Nickel/Titanium/Aluminum (Ni/Ti/Al) metal stacks were deposited on SiC substrates to form Ohmic contact. Circular transfer length method (CTLM) structures were fabricated to characterize contact resistivity. Ion implantation was designed and simulated by Sentraurus technology computer aided design (TCAD) software. Secondary-ion mass spectrometry (SIMS) results show a good match with the simulation results. In addition, SiC ESD protection devices, such as N-type metal-oxide-semiconductor (NMOS), laterally diffused metal-oxide-semiconductor (LDMOS), high-voltage silicon controlled rectifier (HV-SCR) and low-voltage silicon controlled rectifier (LV-SCR), have been designed. Transmission line pulse (TLP) and very fast TLP (VF-TLP) measurements were carried out to characterize their ESD performance. The proposed SiC-based HV-SCR shows the highest failure current on TLP measurement and can be used as an area-efficient ESD protection device. On the other hand, for system-level reliability, this dissertation focuses on the galvanic isolation of high-temperature SiC power modules. Low temperature co-fired ceramics (LTCC) based high-temperature optocouplers were designed and fabricated as galvanic isolators. The LTCC-based high-temperature optocouplers show promising driving capability and steady response speed from 25 ºC to 250 ºC. In order to verify the performance of the high-temperature optocouplers at the system level, LTCC-based gate drivers that utilize the high-temperature optocouplers as galvanic isolators were designed and integrated into a high-temperature SiC-based power module. Finally, the high-temperature power module with integrated LTCC-based gate drivers was characterized by DPTs from 25 ºC to 200 ºC. The power module shows reliable switching performance at elevated temperatures

Chip- and System-Level Reliability on SiC-based Power Modules

The blocking voltage, switching frequency and temperature tolerance of power devices have been greatly improved due to the revolution of wide bandgap (WBG) materials, such as silicon carbide (SiC) and gallium nitride (GaN). Owing to the development of SiC-based power devices, the power rating, operating voltage, and power density of power modules have been significantly improved. However, the reliability of SiC-based power modules has not been fully explored yet. Thus, this dissertation focuses on the chip- and system-level reliability on SiC-based power modules. For chip-level reliability, this work focuses on on-chip SiC ESD protection devices for SiC-based integrated circuits (ICs). In order to develop SiC ESD protection devices, SiC-based Ohmic contact and ion implantation have been studied. Nickel/Titanium/Aluminum (Ni/Ti/Al) metal stacks were deposited on SiC substrates to form Ohmic contact. Circular transfer length method (CTLM) structures were fabricated to characterize contact resistivity. Ion implantation was designed and simulated by Sentraurus technology computer aided design (TCAD) software. Secondary-ion mass spectrometry (SIMS) results show a good match with the simulation results. In addition, SiC ESD protection devices, such as N-type metal-oxide-semiconductor (NMOS), laterally diffused metal-oxide-semiconductor (LDMOS), high-voltage silicon controlled rectifier (HV-SCR) and low-voltage silicon controlled rectifier (LV-SCR), have been designed. Transmission line pulse (TLP) and very fast TLP (VF-TLP) measurements were carried out to characterize their ESD performance. The proposed SiC-based HV-SCR shows the highest failure current on TLP measurement and can be used as an area-efficient ESD protection device. On the other hand, for system-level reliability, this dissertation focuses on the galvanic isolation of high-temperature SiC power modules. Low temperature co-fired ceramics (LTCC) based high-temperature optocouplers were designed and fabricated as galvanic isolators. The LTCC-based high-temperature optocouplers show promising driving capability and steady response speed from 25 ºC to 250 ºC. In order to verify the performance of the high-temperature optocouplers at the system level, LTCC-based gate drivers that utilize the high-temperature optocouplers as galvanic isolators were designed and integrated into a high-temperature SiC-based power module. Finally, the high-temperature power module with integrated LTCC-based gate drivers was characterized by DPTs from 25 ºC to 200 ºC. The power module shows reliable switching performance at elevated temperatures

Electrostatic Discharge

As we enter the nanoelectronics era, electrostatic discharge (ESD) phenomena is an important issue for everything from micro-electronics to nanostructures. This book provides insight into the operation and design of micro-gaps and nanogenerators with chapters on low capacitance ESD design in advanced technologies, electrical breakdown in micro-gaps, nanogenerators from ESD, and theoretical prediction and optimization of triboelectric nanogenerators. The information contained herein will prove useful for for engineers and scientists that have an interest in ESD physics and design

Area Efficient Device Optimization for ESD Protection in High Speed Interface ICs

Electrostatic discharge (ESD) protection is considered as a vital step in integrated circuit (IC) manufacturing process. IC chips are unable to overcome the effects of transient events without adequate discharge protection. Recent trend in the industry has seen the incorporation of system level ESD protection within the IC chip. Incorporating system level on-chip ESD protection often increases cost, degrades circuit performance and consumes layout area which could otherwise be used for improving the circuit performance. These design challenges could be easily overcome if the parasitic components in a circuit were used for ESD protection. Despite the various design challenges, on-chip ESD protection is still desirable as it saves the area on the circuit board by eliminating the traditional ESD protection devices resulting in more compact circuits. Furthermore, using parasitic components while designing on-chip system level ESD protection can save layout area. In order to effectively implement this solution, a study on ESD events, protection circuits and high-speed ICs was carried out. Different types of ESD events and the different models pertaining to ESD events were studied and are discussed in detail. An overview of high-speed integrated circuits was also carried out with emphasis on the protection topologies that are commonly used. The ESD characteristics of parasitic PNP devices in rail-based ESD protection structure was then studied to summarize its viability as a protection circuit. The turn-on or breakdown voltage of the parasitic PNP is studied by technology computer aided design (TCAD) simulations performed in Silvaco software. The breakdown voltage, holding voltage, on resistance and failure current were studied and modeled to maximize ESD protection

Design Of Low-capacitance And High-speed Electrostatic Discharge (esd) Devices For Low-voltage Protection Applications

Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of lowvoltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in iv characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures. Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysiliconbound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode’s design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode’s overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers. The recent industry data indicates the charged device model (CDM) ESD event becomes v increasingly important in today’s manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices’ dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region. Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on vi uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers

Investigations on electromagnetic noises and interactions in electronic architectures : a tutorial case on a mobile system

Electromagnetic interactions become critic in embedded and smart electronic structures. The increase of electronic performances confined in a finite volume or support for mobile applications defines new electromagnetic environment and compatibility configurations (EMC). With canonical demonstrators developed for tutorials and EMC experiences, this paper present basic principles and experimental techniques to investigate and control these severe interferences. Some issues are reviewed to present actual and future scientific challenges for EMC at electronic circuit level