High-order volterra model predictive control and its application to a nonlinear polymerisation process

Model Predictive Control (MPC) has recently found wide acceptance in the process industry, but the existing design and implementation methods are restricted to linear process models. A chemical process involves, however, severe nonlinearity which cannot be ignored in practice. This paper aims to solve this nonlinear control problem by extending MPC to nonlinear models. It develops an analytical framework for nonlinear model predictive control (NMPC), and also offers a third-order Volterra series based nonparametric nonlinear modelling technique for NMPC design which relieves practising engineers from the need for first deriving a physical-principles based model. An on-line realisation technique for implementing the NMPC is also developed. The NMPC is then applied to a Mitsubishi Chemicals polymerisation reaction process. The results show that this nonlinear MPC technique is feasible and very effective. It considerably outperforms linear and low-order Volterra model based methods. The advantages of the approach developed lie not only in control performance superior to existing NMPC methods, but also in relieving practising engineers from the need for deriving an analytical model and then converting it to a Volterra model through which the model can only be obtained up to the second order

Defining correctness conditions for concurrent objects in multicore architectures

Correctness of concurrent objects is defined in terms of conditions that determine allowable relationships between histories of a concurrent object and those of the corresponding sequential object. Numerous correctness conditions have been proposed over the years, and more have been proposed recently as the algorithms implementing concurrent objects have been adapted to cope with multicore processors with relaxed memory architectures. We present a formal framework for defining correctness conditions for multicore architectures, covering both standard conditions for totally ordered memory and newer conditions for relaxed memory, which allows them to be expressed in uniform manner, simplifying comparison. Our framework distinguishes between order and commitment properties, which in turn enables a hierarchy of correctness conditions to be established. We consider the Total Store Order (TSO) memory model in detail, formalise known conditions for TSO using our framework, and develop sequentially consistent variations of these. We present a work-stealing deque for TSO memory that is not linearizable, but is correct with respect to these new conditions. Using our framework, we identify a new non-blocking compositional condition, fence consistency, which lies between known conditions for TSO, and aims to capture the intention of a programmer-specified fence

An approach for identifying brainstem dopaminergic pathways using resting state functional MRI.

Here, we present an approach for identifying brainstem dopaminergic pathways using resting state functional MRI. In a group of healthy individuals, we searched for significant functional connectivity between dopamine-rich midbrain areas (substantia nigra; ventral tegmental area) and a striatal region (caudate) that was modulated by both a pharmacological challenge (the administration of the dopaminergic agonist bromocriptine) and a dopamine-sensitive cognitive trait (an individual's working memory capacity). A significant inverted-U shaped connectivity pattern was found in a subset of midbrain-striatal connections, demonstrating that resting state fMRI data is sufficiently powerful to identify brainstem neuromodulatory brain networks

Optimizing the flash-RAM energy trade-off in deeply embedded systems

Deeply embedded systems often have the tightest constraints on energy consumption, requiring that they consume tiny amounts of current and run on batteries for years. However, they typically execute code directly from flash, instead of the more energy efficient RAM. We implement a novel compiler optimization that exploits the relative efficiency of RAM by statically moving carefully selected basic blocks from flash to RAM. Our technique uses integer linear programming, with an energy cost model to select a good set of basic blocks to place into RAM, without impacting stack or data storage. We evaluate our optimization on a common ARM microcontroller and succeed in reducing the average power consumption by up to 41% and reducing energy consumption by up to 22%, while increasing execution time. A case study is presented, where an application executes code then sleeps for a period of time. For this example we show that our optimization could allow the application to run on battery for up to 32% longer. We also show that for this scenario the total application energy can be reduced, even if the optimization increases the execution time of the code

Polynomial-Time Fence Insertion for Structured Programs

To enhance performance, common processors feature relaxed memory models that reorder instructions. However, the correctness of concurrent programs is often dependent on the preservation of the program order of certain instructions. Thus, the instruction set architectures offer memory fences. Using fences is a subtle task with performance and correctness implications: using too few can compromise correctness and using too many can hinder performance. Thus, fence insertion algorithms that given the required program orders can automatically find the optimum fencing can enhance the ease of programming, reliability, and performance of concurrent programs. In this paper, we consider the class of programs with structured branch and loop statements and present a greedy and polynomial-time optimum fence insertion algorithm. The algorithm incrementally reduces fence insertion for a control-flow graph to fence insertion for a set of paths. In addition, we show that the minimum fence insertion problem with multiple types of fence instructions is NP-hard even for straight-line programs