Analysis and modeling of underfill flow driven by capillary action in flip-chip packaging

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance

Développement de procédés avancés d'encapsulation de composants microélectroniques basés sur les techniques de thermocompression

L'un des grands défis de la recherche et développement est d'optimiser l'ensemble du cycle de fabrication d'un produit microélectronique, depuis sa conception jusqu’à sa tenue mécanique en service. Un objectif essentiel des entreprises était de réduire le temps de cycles d’assemblage afin de minimiser les coûts de production. La phase d’assemblage des composants microélectroniques est l'une des étapes clé qui doit être bien optimisée afin d’atteindre l’objectif de minimisation du temps de cycle. La méthode d'assemblage traditionnelle des puces par refusion (en anglais mass reflow MR) convenait généralement à une fabrication à grand volume, en particulier pour des puces à pas standard d'environ 150 μm. Cependant, la forte demande du marché pour des interconnexions à pas plus fin, pour permettre un nombre d'entrée/sortie (Input/Output : I/O) plus élevé dans un facteur de forme plus petit, a entraîné une transition du processus de la liaison MR conventionnel à l'assemblage par thermocompression (en anglais ThermoCompression Bonding TCB). Bien que le procédé TCB offre un assemblage de plus grande précision et permet l'utilisation des pas d'interconnexion plus fins, il présente également de nouveaux défis. L'un des problèmes majeurs de l'assemblage TCB est qu'il s'agit d'un processus assez long, dans lequel chaque puce doit être passée indépendamment à travers un cycle TCB complet, incluant le chauffage, le maintien de la température et le refroidissement. Cela entraîne une diminution significative de la productivité par rapport au MR. Le débit de production peut être amélioré en réduisant le temps nécessaire pour atteindre les températures de processus requises. Cependant, des variations thermiques peuvent se produire aux interfaces de liaison, entraînant une mauvaise uniformité de température sur la surface de la puce et conduisant à des régions où le point de fusion de la brasure n'est pas atteint. Ainsi, il est extrêmement important de prévoir et contrôler la température réelle à l'interface de liaison afin d’obtenir une bonne uniformité thermique et des joints de brasure sans défaut. C'est dans cette perspective que s'inscrit les travaux menés dans la première partie de la thèse. Le premier objectif de cette étude était donc de déterminer la durée minimum de temps de chauffe nécessaire assurant une uniformité de température optimal et par conséquent des joints de brasure de bonne qualité. Pour atteindre cet objectif, il fallait alors proposer et valider une nouvelle méthodologie pour estimer la température d'interface lors d'un processus TCB. Une évaluation de l'influence de différentes vitesses de chauffe sur la distribution de température à travers la surface de la puce, ainsi que sur la qualité de liaison résultante, a été réalisée à l’aide d’un capteur de type RTD (). Les résultats ont montré que les défauts de brasure observés aux interfaces de liaison peuvent éventuellement être liés à une mauvaise uniformité de température, liée à des vitesses de chauffe élevées. Des variations thermiques acceptables ont été trouvées à une faible vitesse de chauffage de 80°C/s. Par conséquent, pour surmonter les températures de processus élevées et leurs effets néfastes sur la productivité, le développement d'une nouvelle méthode d’assemblage TCB à basse température devient primordiale. Le développement d’une nouvelle méthode de liaison par thermocompression à l'état solide détecteur de température résistif, Resistance Temperature Detector en anglais était donc notre second objectif dans cette étude. Cette méthode est basée sur la création d'une liaison mécanique temporaire initiale au début du processus de packaging (en utilisant une pression à une température inférieure au point de fusion de la brasure). Les joints de iv brasure seront entièrement refondus à la fin du processus de packaging, lorsque les billes de brasure BGA (ball-grid-array) seront brasées au substrat. Cette nouvelle méthode peut surmonter les limitations associées au processus TCB conventionnel, notamment la température élevée, le processus d'assemblage lent et les contraintes mécaniques élevées. Une investigation a été menée pour déterminer les conditions d'assemblage appropriées à appliquer pendant ce processus. Des investigations supplémentaires ont été également menées pour explorer le mécanisme d'assemblage responsable de l’assemblage mécanique temporaire. Les résultats préliminaires de cette méthode sont prometteurs, montrant des joints de brasure de bonne qualité formés en un temps d'assemblage très court (6 secondes) et à des températures bien inférieures au TCB conventionnel (200°C)

The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA)

The cracking between die back edge and top fillet for Flip Chip Ceramic Ball Grid Array (FC-CBGA) package due to thermal cycling have been investigated in this study. Finite Element Analysis (FEA) model was used to analyze the effect of fillet geometry and material properties of underfill upon stresses along the die back edge. The thermo-mechanical properties of commercial underfill were obtained by using Thermal Mechanical Analyzer (TMA) and Dynamic Mechanical Analyzer (DMA) as the input for the simulation. Die stress distribution for different fillet height and width were generated to depict variation of stress due thermal loading and the variations of tensile stress were discussed for parameter optimization. The effect of different underfill material properties were discussed as well for thermal stress reliability improvement

Thermo-Mechanical Reliability and Electrical Performance of Indium Interconnects and Under Bump Metallization

This thesis presents reliability analysis of indium interconnects and Under Bump Metallization (UBM) in flip chip devices. Flip chip assemblies with the use of bump interconnections are frequently used, especially in high density, three-dimensional electronic devices. Currently there are many methods for interconnect bumping, all of which require UBM. The UBM is required for interconnection, diffusion resistance and quality electrical contact between substrate and device. Bonded silicon test vehicles were comprised of Indium bumps and three UBM compositions: Ti/Ni/Au (200\xc5/1000\xc5/500\xc5), Ti/Ni (200\xc5/1000\xc5), Ni (1000\xc5). UBM and indium were deposited by evaporation and exposed to unbiased accelerated temperature cycling(-55°C to 125°C, 15°C/min ramp rate). Finite Element Analysis (FEA) simulations were used to gain understanding of non-linear strain behavior of indium interconnects during temperature cycling. Experimental testing coupled with FEA simulations facilitated cycle-to-failure calculations. FEA results show plastic strain concentrations within indium bump below failure limits. It has been demonstrated that fabrication of Ti/Ni/Au, Ti/Ni, and Ni UBM stacks performed reliably within infant mortality failure region

LTCC packaging for Lab-on-a-chip application

LTCC -pakkaus Lab-on-a-chip -sovellukseen. Tiivistelmä. Tässä työssä suunniteltiin, valmistettiin ja testattiin uusi pakkaustekniikka ”Lab-on-a-chip” (LOC) -sovellukseen. Pakkaus tehtiin pii-mikrosirulle, jolla voidaan mitata solujen kiinnittymistä sirun pintaan solujen elinkelpoisuuden indikaattorina. Luotettavuustestaukset tehtiin daisy-chain -resistanssimittauksilla solunkasvatusolosuhteissa. Lisäksi työssä selvitettiin LTCC- ja ”Lab-on-a-chip” -teknologioiden perusteet teoreettiselta pohjalta. Mikrosirun pakkauksessa käytettiin joustavaa LTCC-teknologiaa. Sähköisiin kontakteihin ja niiden suojauksiin käytettiin sekä johtavia että eristäviä epoksi-liimoja. LOC-sovelluksiin on tärkeää kehittää uusia pakkausmenetelmiä jotta näiden laitteiden kaikki ominaisuudet saadaan toimimaan luotettavasti. Pakkaus testattiin samoissa olosuhteissa missä sitä tullaan käyttämään ja pakkaus kesti kaikki nämä haasteet. Lisäksi esitetty valmistusprosessi on sellainen, että sitä voidaan käyttää myös muihin ”Lab-on-a-chip” -sovelluksiin.Abstract. This work presents design, manufacturing and testing of new packaging method for Lab-on-a-chip (LOC) application. Packaging was made for silicon microchip which can measure cell adhesion on chips surface as indication of cell viability. Reliability testing was done with daisy-chain resistance measurement in real conditions. Moreover basic theory of LTCC and Lab-on-a-chip technology is presented. Resilient LTCC technology was used for packaging material and conductive/insulating epoxies were applied for electrical contacts and barriers against the environment. It is fundamentally important to develop new packaging methods for LOC applications, so all the properties can be utilized reliably. Packaging was tested under the cell growth conditions and the package showed to withstand all these challenges. Moreover the presented packaging method is possible to use also in other Lab-on-a-chip applications

Evaluation, Optimization,and Reliability of No-flow Underfill Process

This research details the development of a novel process for four commercially available no-flow fluxing underfills for use with flip chip on FR4 substrates. The daisy chain test die was used such that two point resistance measurements could be used to determine the integrity of the solder interconnects post reflow. The impact of the underfill dispensing pattern on underfill void formation is determined in a full factorial dispense DOE that includes two factors: pattern and speed. Evaluation metrics include underfill material voiding and fillet shape. The impact of the placement process is determined in a second full factorial DOE involving three factors at two levels each: dispense pattern, placement force, and dwell time. Metrics include interconnect yield and underfill voiding. The results of these DOEs are used to select an optimal placement process for each material to be used for the remaining reflow experiments. The process developed is a novel approach to no-flow processing; the material is dispensed to the side of the bond site and allowed to flow under the chip after placement by capillary action during the early stages of reflow. This development allows for void free assemblies using no-flow materials. Reflow parameters are investigated using a parametric approach. The following parameters are varied at 2 levels individually off a baseline profile: Peak Temperature, Time > 183 oC, Peak Ramp Rate, Soak Time, and Soak Temperature. A ranking was developed for each material based on the observable metrics: interconnect yield, underfill material voiding, two point resistance, and a grain area fraction term. The results were used to select an optimal assembly process for each material. Test boards were assembled in replicates of 30 according to the optimal process for each material, and AATC -40 to 125 oC thermal cycling test was performed. The MTTF for these assemblies has exceeded 3000 cycles; the void free process successfully avoids premature failure due to solder extrusion into voids. Further process development work has demonstrated that the process is scalable to larger area array die and other edge dispense patterns have also been demonstrated to result in void free assemblies.M.S.Committee Chair: Daniel Baldwin; Committee Member: Steven Danyluk; Committee Member: Suresh Sitarama

Experimental Study of Novel Materials and Module for Cryogenic (4K) Superconducting Multi-Chip Modules

The objectives of this proposal are to understand the science and technology of interfaces in the packaging of superconducting electronic (SCE) multichip modules (MCMs) at 4 K. The thermal management issue of the current SCE-MCMs was examined and the package assembly was optimized. A novel thermally conducting and electrically insulating nano-engineered polymer was developed for the thermal management of SCE-MCMs for 4 K cryogenic packaging. Finally, the nano-engineered polymer was integrated as underfill in a SCE-MCM and the thermal and electrical performance of SCE-MCM was demonstrated at 4 K. Niobium based superconducting electronics (SCE) are the fastest known digital logic which operate at 100GHz and greater. Nevertheless, the performance of the SCE device depends on the temperature of the SCE integrated circuits being maintained between 4.2 - 4.25 K. Additionally, as semiconductors are slowly approaching their performance limitations the SCE devices are viewed as a viable alternative for high end computing and commercial wireless applications. However, the successful implementation of SCE\u27s requires the demonstration of these devices in multichip module (MCM) architecture. Thus the stringent thermal constraint and the complex MCM architecture require an innovative method for thermal management which is addressed by the current research

Peripheral soldering of flip chip joints on passive RFID tags

Flip chip is the main component of a RFID tag. It is used in billions each year in electronic packaging industries because of its small size, high performance and reliability as well as low cost. They are used in microprocessors, cell phones, watches and automobiles. RFID tags are applied to or incorporated into a product, animal, or person for identification and tracking using radio waves. Some tags can be read from several meters away or even beyond the line of sight of the reader. Passive RFID tags are the most common type in use that employ external power source to transmit signals. Joining chips by laser beam welding have wide advantages over other methods of joining, but they are seen limited to transparent substrates. However, connecting solder bumps with anisotropic conductive adhesives (ACA) produces majority of the joints. A high percentage of them fail in couple of months, particularly when exposed to vibration. In the present work, failure of RFID tags under dynamic loading or vibration was studied; as it was identified as one of the key issue to explore. Earlier investigators focused more on joining chip to the bump, but less on its assembly, i.e., attaching to the substrate. Either of the joints, between chip and bump or between antenna and bump can fail. However, the latter is more vulnerable to failure. Antenna is attached to substrate, relatively fixed when subjected to oscillation. It is the flip chip not the antenna moves during vibration. So, the joint with antenna suffers higher stresses. In addition to this, the strength of the bonding agent i.e., ACA also much smaller compared to the metallic bond at the other end of the bump. Natural frequency of RFID tags was calculated both analytically and numerically, found to be in kilohertz range, high enough to cause resonance. Experimental investigations were also carried out to determine the same. However, the test results for frequency were seen to be in hundred hertz range, common to some applications. It was recognized that the adhesive material, commonly used for joining chips, was primarily accountable for their failures. Since components to which the RFID tags are attached to experience low frequency vibration, chip joints fail as they face resonance during oscillation. Adhesives having much lower modulus than metals are used for attaching bumps to the substrate antennas, and thus mostly responsible for this reduction in natural frequency. Poor adhesive bonding strength at the interface and possible rise in temperature were attributed to failures under vibration. In order to overcome the early failure of RFID tag joints, Peripheral Soldering, an alternative chip joining method was devised. Peripheral Soldering would replace the traditional adhesive joining by bonding the peripheral surface of the bump to the substrate antenna. Instead of joining solder bump directly to the antenna, holes are to be drilled through antenna and substrate. S-bond material, a less familiar but more compatible with aluminum and copper, would be poured in liquid form through the holes on the chip pad. However, substrates compatible to high temperature are to be used; otherwise temperature control would be necessary to avoid damage to substrate. This S-bond would form metallic joints between chip and antenna. Having higher strength and better adhesion property, S-bond material provides better bonding capability. The strength of a chip joined by Peripheral Soldering was determined by analytical, numerical and experimental studies. Strength results were then compared to those of ACA. For a pad size of 60 micron on a 0.5 mm square chip, the new chip joints with Sbond provide an average strength of 0.233N analytically. Numerical results using finite element analysis in ANSYS 11.0 were about 1% less than the closed form solutions. Whereas, ACA connected joints show the maximum strength of 0.113N analytically and 0.1N numerically. Both the estimates indicate Peripheral Soldering is more than twice stronger than adhesive joints. Experimental investigation was carried out to find the strength attained with S-bond by joining similar surfaces as those of chip pad and antenna, but in larger scale due to limitation in facilities. Results obtained were moderated to incorporate the effect of size. Findings authenticate earlier predictions of superior strengths with S-bond. A comparison with ACA strength, extracted from previous investigations, further indicates that S-bond joints are more than 10 times stronger. Having higher bonding strength than in ACA joints, Peripheral Soldering would provide better reliability of the chip connections, i.e., RFID tags. The benefits attained would pay off complexities involved in tweaking

A THERMOMECHANICAL FATIGUE LIFE PREDICTION METHODOLOGY FOR BALL GRID ARRAY COMPONENTS WITH REWORKABLE UNDERFILL

Underfill materials were originally developed to improve the thermo-mechanical reliability of flip-chip devices due to the large coefficient of thermal expansion (CTE) mismatch between the silicon die and substrate. More recently, underfill materials, specifically reworkable underfills, have been used to improve reliability of second level interconnects in ball grid array (BGA) packages in harsh end-use environments such as automotive, military and aerospace. In these environments, electronic components are exposed to mechanical shock, vibration, and large fluctuations in temperatures. Although reworkable underfills improve the reliability of BGA components under mechanical shock and vibration, some reworkable underfills have been shown to reduce reliability during thermal cycling environments. Consequently, this research employs experimental and numerical approaches to investigate the impact of reworkable underfill materials on thermomechanical fatigue life of solder joints in BGA packages. In the first section of the analysis, material characterization of a reworkable underfill is performed to determine appropriate material models for reworkable underfills. In the second analysis section, a variety of underfill materials with different properties are exposed to harsh and benign thermal cycles to determine the stress state responsible for reducing fatigue life of solder joints in BGA packages. In the final analysis section, simulations are performed on the BGAs with reworkable underfill to develop a fatigue life predication methodology that implements a modified mode separation scheme. The model developed in this work provides a working fatigue life approach for BGA packages with reworkable underfills exposed to thermal loading. The results of this study can be utilized by the automotive, military, and aerospace industries to optimize underfill material selection process and provide reliability assessment of BGA components in real world environments

Effects of Aspect Ratio in Moulded Packaging Considering Fluid/Structure Interaction: A CFD Modelling Approach

The fluid/structure interaction (FSI) investigations of stacked chip in encapsulation process of moulded underfill packaging using the two-way Coupling method with ANSYS Fluent and ANSYS Structural solvers are presented. The FSI study is executed with different aspect ratio of stacked chip on the mould filling during the encapsulation process. The simulation results in the FSI study is well validated with experimental setup. The epoxy moulding compound (EMC) and structure (chip) interaction is analyzed for better understanding the FSI phenomenon.Von Mises stresses experienced by the chip also be monitored for risk of chip cracking. The proposed analysis is anticipated to be a recommendation in the chip design and improvement of 3D integration packages