Wideband Interleaved Vector Modulators for 5G Wireless Communications

Next generation wireless communication systems such as fifth generation mobile communications and high throughput satellites have promised a step increase in the rate at which digital data can be transmitted. This requires wideband modulators consisting of high speed digital to analogue converters and RF upconverters to generate the wideband signal of interest. In this paper we demonstrate a scheme to generate a wide bandwidth modulated signal by bandwidth interleaving multiple modulators of narrower bandwidths. The proposed scheme is experimentally validated with measured results on an 8PSK signals of symbol rate 80 MSPS with modulation characteristics in accordance with DVB-S2 standard

Digital signal splitting among multiple DACs for analog bandwidth interleaving (ABI)

A novel concept called analog bandwidth interleaving (ABI) has been recently introduced in order to overcome bandwidth limitations of digital-to-analog converters (DACs) by interleaving the output signals of multiple DACs in the frequency domain. We present for the first time the fundamental interdependencies between bandwidth, sample rate, the number of samples, and the local oscillator frequencies for ABI-DACs. Furthermore, a mathematical expression for the splitting of the digital signal among multiple DACs is presented. Simulations for an exemplary ABI-DAC highlight the interdependencies between the system parameters and difficulties concerning integer solutions

Entwicklung integrierter Treiber-Verstärker für optische Übertragungssysteme in SiGe-Bipolar-Technologie

Die vorliegende Arbeit beschäftigt sich mit der Entwicklung von Treiberverstärkern in SiGe-Bipolar-Technologie für optische Übertragungsstrecken. Die Zielspezifikationen solcher Treiber fordern nicht nur hohe Bandbreiten bzw. Datenraten, sondern auch große Ausgangsspannungshübe im Vergleich zur Durchbruchsspannung der Transistoren. Darüber hinaus wird je nach Anwendung eine hohe Linearität angestrebt. Das Ziel der Arbeit ist die Entwicklung neuer Methoden zur Entwicklung von Treiberverstärkern, die das Erreichen dieser Anforderungen ermöglichen. Treiberschaltungen zeichnen sich besonders durch die großen Spannungshübe aus, die wiederum große Ströme bedingen. Die dadurch entstehenden, großen Verlustleistungsdichten erfordern eine genaue thermische Analyse der Schaltungen. Außerdem werden Schaltungskonzepte vorgestellt, um die Leistungsaufnahme der Treiberschaltungen zu reduzieren. Bedingt durch die großen Ströme in Verbindung mit parasitären Induktivitäten sind Treiberschaltungen besonders anfällig für Instabilitäten. Daher wird die Analyse und Dimensionierung der Schaltungen im Hinblick auf ihre Stabilität ausführlich behandelt. Die Anwendung der neuen Methoden und Konzepte wird am Beispiel der Entwicklung von drei grundlegend unterschiedlichen Treiberschaltungen demonstriert, die jeweils den Stand der Technik erweitern.The subject of this thesis is the development of driver amplifiers in SiGe bipolar technology for optical communication links. The target specifications of such drivers require not only high bandwidths and data rates, but also high output voltage swings compared with the breakdown voltage of the transistors. Furthermore, depending on the application, a high linearity is aimed at. The goal of this work is the development of new methods for the development of driver amplifiers to facilitate the achievement of these objectives. Driver circuits feature in particular high voltage swings and consequently require high currents. The corresponding high power densities require a precise thermal analysis of the circuits. Furthermore, circuit concepts to reduce the power consumption of driver circuits are presented. Because of the high currents in conjunction with parasitic inductances driver circuits are prone for instabilities. Hence, the analysis of the circuits with regard to their stability is elaborately examined. The application of the new methods and concepts is demonstrated at the example of the development of three fundamentally different driver circuits which in each case expand the state of the art

Design techniques for low-power multi-GS/s analog-to-digital converters

Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off of the number of the channels and the sampling rate in each channel. Phase misalignment and channel mismatch must be considered too. Second, timing accuracy, especially dynamic jitter of sampling clock becomes a major concern at ultra-high frequency, and certain techniques must be taken to address it. Finally, to achieve low power consumption, Flash architecture is not suitable to serve as the sub-ADC, and a low-power sub-ADC that can work at relatively high speed need to be designed. A single channel, asynchronous successive approximation (SA) ADC with improved feedback delay has been fabricated in 40nm CMOS. Compared with a conventional SA structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SA-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator’s quantization delay, as the digital logic delay is eliminated. Measurement results of the 40nm-CMOS SA-ADC achieves peak SNDR of 32.9dB at 1GS/s and 30.5dB at 1.25GS/s, consuming 5.28mW and 6.08mW respectively, leading to FoM of 148fJ/conversion-step and 178fJ/conversion-step, in a core area less than 170µm by 85µm. Based on the previous work of sub-ADC, a 12-GS/s 5-b 50-mW ADC is designed in 40nm CMOS with 8 time-interleaved channels of Flash-SA hybrid structure each running at 1.5GS/s. A modified bootstrapped switch is used in the track-and-hold circuit, introducing a global clock signal to synchronize the sampling instants of each individual channel, therefore improve the phase alignment and reduce distortion. The global clock is provided by a CML buffer which is injected by off-chip low-noise sine-wave signal, so that the RMS dynamic jitter is low for better ENOB performance. Measurement results show that the 12GS/s ADC can achieve a SNDR of 25.8dB with the input signal frequency around DC and 22.8dB around 2GHz, consuming 32.1mW, leading to FoM of 237.3fJ/conversion-step, in a core area less than 800µm by 500µm

Teaching Your Wireless Card New Tricks: Smartphone Performance and Security Enhancements Through Wi-Fi Firmware Modifications

Smartphones come with a variety of sensors and communication interfaces, which make them perfect candidates for mobile communication testbeds. Nevertheless, proprietary firmwares hinder us from accessing the full capabilities of the underlying hardware platform which impedes innovation. Focusing on FullMAC Wi-Fi chips, we present Nexmon, a C-based firmware modification framework. It gives access to raw Wi-Fi frames and advanced capabilities that we found by reverse engineering chips and their firmware. As firmware modifications pose security risks, we discuss how to secure firmware handling without impeding experimentation on Wi-Fi chips. To present and evaluate our findings in the field, we developed the following applications. We start by presenting a ping-offloading application that handles ping requests in the firmware instead of the operating system. It significantly reduces energy consumption and processing delays. Then, we present a software-defined wireless networking application that enhances scalable video streaming by setting flow-based requirements on physical-layer parameters. As security application, we present a reactive Wi-Fi jammer that analyses incoming frames during reception and transmits arbitrary jamming waveforms by operating Wi-Fi chips as software-defined radios (SDRs). We further introduce an acknowledging jammer to ensure the flow of non-targeted frames and an adaptive power-control jammer to adjust transmission powers based on measured jamming successes. Additionally, we discovered how to extract channel state information (CSI) on a per-frame basis. Using both SDR and CSI-extraction capabilities, we present a physical-layer covert channel. It hides covert symbols in phase changes of selected OFDM subcarriers. Those manipulations can be extracted from CSI measurements at a receiver. To ease the analysis of firmware binaries, we created a debugging application that supports single stepping and runs as firmware patch on the Wi-Fi chip. We published the source code of our framework and our applications to ensure reproducibility of our results and to enable other researchers to extend our work. Our framework and the applications emphasize the need for freely modifiable firmware and detailed hardware documentation to create novel and exciting applications on commercial off-the-shelf devices

Técnicas de pré-codificação para sistemas multicelulares coordenados

Doutoramento em TelecomunicaçõesCoordenação Multicélula é um tópico de investigação em rápido crescimento e uma solução promissora para controlar a interferência entre células em sistemas celulares, melhorando a equidade do sistema e aumentando a sua capacidade. Esta tecnologia já está em estudo no LTEAdvanced sob o conceito de coordenação multiponto (COMP). Existem várias abordagens sobre coordenação multicélula, dependendo da quantidade e do tipo de informação partilhada pelas estações base, através da rede de suporte (backhaul network), e do local onde essa informação é processada, i.e., numa unidade de processamento central ou de uma forma distribuída em cada estação base. Nesta tese, são propostas técnicas de pré-codificação e alocação de potência considerando várias estratégias: centralizada, todo o processamento é feito na unidade de processamento central; semidistribuída, neste caso apenas parte do processamento é executado na unidade de processamento central, nomeadamente a potência alocada a cada utilizador servido por cada estação base; e distribuída em que o processamento é feito localmente em cada estação base. Os esquemas propostos são projectados em duas fases: primeiro são propostas soluções de pré-codificação para mitigar ou eliminar a interferência entre células, de seguida o sistema é melhorado através do desenvolvimento de vários esquemas de alocação de potência. São propostas três esquemas de alocação de potência centralizada condicionada a cada estação base e com diferentes relações entre desempenho e complexidade. São também derivados esquemas de alocação distribuídos, assumindo que um sistema multicelular pode ser visto como a sobreposição de vários sistemas com uma única célula. Com base neste conceito foi definido uma taxa de erro média virtual para cada um desses sistemas de célula única que compõem o sistema multicelular, permitindo assim projectar esquemas de alocação de potência completamente distribuídos. Todos os esquemas propostos foram avaliados em cenários realistas, bastante próximos dos considerados no LTE. Os resultados mostram que os esquemas propostos são eficientes a remover a interferência entre células e que o desempenho das técnicas de alocação de potência propostas é claramente superior ao caso de não alocação de potência. O desempenho dos sistemas completamente distribuídos é inferior aos baseados num processamento centralizado, mas em contrapartida podem ser usados em sistemas em que a rede de suporte não permita a troca de grandes quantidades de informação.Multicell coordination is a promising solution for cellular wireless systems to mitigate inter-cell interference, improving system fairness and increasing capacity and thus is already under study in LTE-A under the coordinated multipoint (CoMP) concept. There are several coordinated transmission approaches depending on the amount of information shared by the transmitters through the backhaul network and where the processing takes place i.e. in a central processing unit or in a distributed way on each base station. In this thesis, we propose joint precoding and power allocation techniques considering different strategies: Full-centralized, where all the processing takes place at the central unit; Semi-distributed, in this case only some process related with power allocation is done at the central unit; and Fulldistributed, where all the processing is done locally at each base station. The methods are designed in two phases: first the inter-cell interference is removed by applying a set of centralized or distributed precoding vectors; then the system is further optimized by centralized or distributed power allocation schemes. Three centralized power allocation algorithms with per-BS power constraint and different complexity tradeoffs are proposed. Also distributed power allocation schemes are proposed by considering the multicell system as superposition of single cell systems, where we define the average virtual bit error rate (BER) of interference-free single cell system, allowing us to compute the power allocation coefficients in a distributed manner at each BS. All proposed schemes are evaluated in realistic scenarios considering LTE specifications. The numerical evaluations show that the proposed schemes are efficient in removing inter-cell interference and improve system performance comparing to equal power allocation. Furthermore, fulldistributed schemes can be used when the amounts of information to be exchanged over the backhaul is restricted, although system performance is slightly degraded from semi-distributed and full-centralized schemes, but the complexity is considerably lower. Besides that for high degrees of freedom distributed schemes show similar behaviour to centralized ones

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities