Clock Generation Design for Continuous-Time Sigma-Delta Analog-To-Digital Converter in Communication Systems

Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (ΣΔ) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass ΣΔ which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system. Clock generation, a major building block in radio frequency (RF) integrated circuits (ICs), usually uses a phase-locked loop (PLL) to provide the required clock frequency to modulate/demodulate the informative signals. This work explores the design of clock generation in RF ICs. First, a 2-16 GHz frequency synthesizer is proposed to provide the sampling clocks for a programmable continuous-time bandpass sigma-delta (ΣΔ) modulator in a software radio receiver system. In the frequency synthesizer, a single-sideband mixer combines feed-forward and regenerative mixing techniques to achieve the wide frequency range. Furthermore, to optimize the excess loop delay in the wideband system, a phase-tunable clock distribution network and a clock-controlled quantizer are proposed. Also, the false locking of regenerative mixing is solved by controlling the self-oscillation frequency of the CML divider. The proposed frequency synthesizer performs excellent jitter performance and efficient power consumption. Phase noise and quadrature phase accuracy are the common tradeoff in a quadrature voltage-controlled oscillator. A larger coupling ratio is preferred to obtain good phase accuracy but suffer phase noise performance. To address these fundamental trade-offs, a phasor-based analysis is used to explain bi-modal oscillation and compute the quadrature phase errors given by inevitable mismatches of components. Also, the ISF is used to estimate the noise contribution of each major noise source. A CSD QVCO is first proposed to eliminate the undesired bi-modal oscillation and enhance the quadrature phase accuracy. The second work presents a DCC QVCO. The sophisticated dynamic current-clipping coupling network reduces injecting noise into LC tank at most vulnerable timings (zero crossing points). Hence, it allows the use of strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed DCC QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1MHz offset from a 5GHz carrier. The QVCO consumes 4.2mW with a 1-V power supply, resulting in an outstanding Figure of Merit (FoM) of 189 dBc/Hz. Frequency divider is one of the most power hungry building blocks in a PLL-based frequency synthesizer. The complementary injection-locked frequency divider is proposed to be a low-power solution. With the complimentary injection schemes, the dividers can realize both even and odd division modulus, performing a more than 100% locking range to overcome the PVT variation. The proposed dividers feature excellent phase noise. They can be used for multiple-phase generation, programmable phase-switching frequency dividers, and phase-skewing circuits

Beyond Modelocking: High Repetition-Rate Frequency Combs Derived from a Continuous-Wave Laser

Optical frequency combs based on modelocked lasers have revolutionized precision metrology by facilitating measurements of optical frequencies, with implications both for fundamental scientific questions and for applications such as fast, broadband spectroscopy. In this thesis, I describe advances in the generation of frequency combs without modelocking in platforms with smaller footprints and higher repetition rates, with the ultimate goal of bringing frequency combs to new applications in a chip-integrated package. I discuss two approaches for comb generation: parametric frequency conversion in Kerr microresonators and active electro-optic modulation of a continuous-wave laser. After introducing microresonator-based frequency combs (microcombs), I discuss two specific developments in microcomb technology: First, I describe a new, extremely reliable method for generation of soliton pulses through the use of a phase-modulated pump laser. This technique eliminates the dependence on initial conditions that was formerly a universal feature of these experiments, presenting a solution to a significant technical barrier to the practical application of microcombs. Second, I present observations of soliton crystal states with highly structured `fingerprint' optical spectra that correspond to ordered pulse trains exhibiting crystallographic defects. These pulse trains arise through interaction of solitons with avoided mode crossings in the resonator spectrum. I also discuss generation of Kerr soliton combs in the Fabry-Perot (FP) geometry, with a focus on the differences between the FP geometry and the ring geometry that has been the choice of most experimenters to date. Next, I discuss combs based on electro-optic modulation. I introduce the operational principle, and then describe the first self-referencing of a frequency comb of this kind and a proof-of-principle application experiment. Finally, I discuss a technique for reducing the repetition rate of a high repetition-rate frequency comb. This will be a useful post-processing step for applications that require either high pulse energy, such as nonlinear spectral broadening for ƒ-2ƒ self-referencing, or fine spectral resolution

Digital Phase Locked-Loop With Wide Tuning Range And Dynamic Phase Shift

For decades, Phase Lock Loop (PLL) has been widely used in numerous systems, such as telecommunications and digital design, where it plays significant role in improving overall system timing. Moving forward, with the latest revolution towards System-on-chip technology (SOC), the need of PLL in the form of Integrated Circuits has been growing tremendously. Core of this research is to design a PLL with wide tuning range and dynamic phase shift feature, which is implemented in the Integrated Circuits level. In line with fierce competition and fast-paced semiconductor industry, PLL design with above features are definitely most sought after, as it will tremendously reduce turn-around time, cost and effort for a project. Wide tuning range is achieved by introducing new Voltage Control Oscillator architecture, which will be able to provide wide tuning range without using very high KVCO. The new architecture proposed in this project is in differential input structure and consists of MOSFETs and capacitors; thus the area of implementation is small.Besides, extra feature which is proposed in this PLL is Dynamic Phase Shift feature. Dynamically tunable phase shift is important since the accuracy of the phase could be adjusted without having to reprogram the PLL, thus saving a lot of time. Dynamic Phase Shift feature is a new idea, which its design is implemented by using UP/DOWN counters, OR and AND gates. The complete design includes synchronous system design work such as state machine, diagram and truth table for system simplification. This proposed design achieved all specifications with wide-tuning range of 600MHz to 1300MHz is achieved with control voltage swing of 0.9V to 1.5V. Besides, the maximum static phase error measured in the simulation is 66ps, which is smaller than 200ps specification. Highest Period Jitter is 181ps while Cycle-to-Cycle Jitter is 55ps. Both types of jitter are within specification; lower than 300ps. Dynamic Phase Shift also successfully implemented where the UP/DN signal as the control to indicate either the phase is to be shifted up or down

A Low-Power BFSK/OOK Transmitter for Wireless Sensors

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation

Harnessing optical micro-combs for microwave photonics

In the past decade, optical frequency combs generated by high-Q micro-resonators, or micro-combs, which feature compact device footprints, high energy efficiency, and high-repetition-rates in broad optical bandwidths, have led to a revolution in a wide range of fields including metrology, mode-locked lasers, telecommunications, RF photonics, spectroscopy, sensing, and quantum optics. Among these, an application that has attracted great interest is the use of micro-combs for RF photonics, where they offer enhanced functionalities as well as reduced size and power consumption over other approaches. This article reviews the recent advances in this emerging field. We provide an overview of the main achievements that have been obtained to date, and highlight the strong potential of micro-combs for RF photonics applications. We also discuss some of the open challenges and limitations that need to be met for practical applications.Comment: 32 Pages, 13 Figures, 172 Reference

External Cavity Mode-locked Semiconductor Lasers For The Generation Of Ultra-low Noise Multi-gigahertz Frequency Combs And Applications In Multi-heterodyne Detection Of Arbitrary Optical Waveforms

The construction and characterization of ultra-low noise semiconductor-based mode-locked lasers as frequency comb sources with multi-gigahertz combline-to-combline spacing is studied in this dissertation. Several different systems were built and characterized. The first of these systems includes a novel mode-locking mechanism based on phase modulation and periodic spectral filtering. This mode-locked laser design uses the same intra-cavity elements for both mode-locking and frequency stabilization to an intra-cavity, 1,000 Finesse, Fabry-Pérot Etalon (FPE). On a separate effort, a mode-locked laser based on a Slab-Coupled Optical Waveguide Amplifier (SCOWA) was built. This system generates a pulse-train with residual timing jitter o

Ultra-Low Power Wake Up Receiver For Medical Implant Communications Service Transceiver

This thesis explores the specific requirements and challenges for the design of a dedicated wake-up receiver for medical implant communication services equipped with a novel “uncertain-IF†architecture combined with a high – Q filtering MEMS resonator and a free running CMOS ring oscillator as the RF LO. The receiver prototype, implements an IBM 0.18μm mixed-signal 7ML RF CMOS technology and achieves a sensitivity of -62 dBm at 404MHz while consuming \u3c100 μW from a 1 V supply

Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References.

Microelectromechanical systems (MEMS) have great potential in realizing chip-scale integrated devices for energy-efficient analog spectrum processing. This thesis presents the development of a new class of MEMS resonators and filters integrated with CMOS readout circuits for RF front-ends and integrated timing applications. Circuit-level innovations coupled with new device designs allowed for realizing integrated systems with improved performance compared to standalone devices reported in the literature. The thesis is comprised of two major parts. The first part of the thesis is focused on developing integrated MEMS timing devices. Fused silica is explored as a new structural material for fabricating high-Q vibrating micromechanical resonators. A piezoelectric-on-silica MEMS resonator is demonstrated with a high Q of more than 20,000 and good electromechanical coupling. A low phase noise CMOS reference oscillator is implemented using the MEMS resonator as a mechanical frequency reference. Temperature-stable operation of the MEMS oscillator is realized by ovenizing the platform using an integrated heater. In an alternative scheme, the intrinsic temperature sensitivity of MEMS resonators is utilized for temperature sensing, and active compensation for MEMS oscillators is realized by oven-control using a phase-locked loop (PLL). CMOS circuits are implemented for realizing the PLL-based low-power oven-control system. The active compensation technique realizes a MEMS oscillator with an overall frequency drift within +/- 4 ppm across -40 to 70 °C, without the need for calibration. The CMOS PLL circuits for oven-control is demonstrated with near-zero phase noise invasion on the MEMS oscillators. The properties of PLL-based compensation for realizing ultra-stable MEMS frequency references are studied. In the second part of the thesis, RF MEMS devices, including tunable capacitors, high-Q inductors, and ohmic switches, are fabricated using a surface micromachined integrated passive device (IPD) process. Using this process, an integrated ultra-wideband (UWB) filter has been demonstrated, showing low loss and a small form factor. To further address the issue of narrow in-band interferences in UWB communication, a tunable MEMS bandstop filter is integrated with the bandpass filter with more than an octave frequency tuning range. The bandstop filter can be optionally switched off by employing MEMS ohmic switches co-integrated on the same chip.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/109069/1/zzwu_1.pd

Energy-Efficient Wireless Connectivity and Wireless Charging For Internet-of-Things (IoT) Applications

During the recent years, the Internet-of-Things (IoT) has been rapidly evolving. It is indeed the future of communication that has transformed Things of the real world into smarter devices. To date, the world has deployed billions of “smart” connected things. Predictions say there will be 10’s of billions of connected devices by 2025 and in our lifetime we will experience life with a trillion-node network. However, battery lifespan exhibits a critical barrier to scaling IoT devices. Replacing batteries on a trillion-sensor scale is a logistically prohibitive feat. Self-powered IoT devices seems to be the right direction to stand up to that challenge. The main objective of this thesis is to develop solutions to achieve energy-efficient wireless-connectivity and wireless-charging for IoT applications. In the first part of the thesis, I introduce ultra-low power radios that are compatible with the Bluetooth Low-Energy (BLE) standard. BLE is considered as the preeminent protocol for short-range communications that support transmission ranges up to 10’s of meters. Number of low power BLE transmitter (TX) and receiver (RX) architectures have been designed, fabricated and tested in different planar CMOS and FinFET technologies. The low power operation is achieved by combining low power techniques in both the network and physical layers, namely: backchannel communication, duty-cycling, open-loop transmission/reception, PLL-less architectures, and mixer-first architectures. Further novel techniques have been proposed to further reduce the power the consumption of the radio design, including: a fast startup time and low startup energy crystal oscillators, an antenna-chip co-design approach for quadrature generation in the RF path, an ultra-low power discrete-time differentiator-based Gaussian Frequency Shift Keying (GFSK) demodulation scheme, an oversampling GFSK modulation/demodulation scheme for open loop transmission/reception and packet synchronization, and a cell-based design approach that allows automation in the design of BLE digital architectures. The implemented BLE TXs transmit fully-compliant BLE advertising packet that can be received by commercial smartphone. In the second part of the thesis, I introduce passive nonlinear resonant circuits to achieve wide-band RF energy harvesting and robust wireless power transfer circuits. Nonlinear resonant circuits modeled by the Duffing nonlinear differential equation exhibit interesting hysteresis characteristics in their frequency and amplitude responses that are exploited in designing self-adaptive wireless charging systems. In the magnetic-resonance wireless power transfer scenario, coupled nonlinear resonators are proposed to maintain the power transfer level and efficiency over a range of coupling factors without active feedback control circuitry. Coupling factor depends on the transmission distance, lateral, and angular misalignments between the charging pad and the device. Therefore, nonlinear resonance extends the efficient charging zones of a wireless charger without the requirement for a precise alignment.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169842/1/omaratty_1.pd

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results