Towards an optimised VLSI design algorithm for the constant matrix multiplication problem

The efficient design of multiplierless implementations of constant matrix multipliers is challenged by the huge solution search spaces even for small scale problems. Previous approaches tend to use hill-climbing algorithms risking sub-optimal results. The proposed algorithm avoids this by exploring parallel solutions. The computational complexity is tackled by modelling the problem in a format amenable to genetic programming and hardware acceleration. Results show an improvement on state of the art algorithms with future potential for even greater savings

Joint Optimization of Low-power DCT Architecture and Effcient Quantization Technique for Embedded Image Compression

International audienceThe Discrete Cosine Transform (DCT)-based image com- pression is widely used in today's communication systems. Signi cant research devoted to this domain has demonstrated that the optical com- pression methods can o er a higher speed but su er from bad image quality and a growing complexity. To meet the challenges of higher im- age quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI archi- tecture of the DCT algorithm and an e cient quantization technique. Our approach is, rstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a recon gurable quantization method is presented to e ectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and com- parisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement

Optimization Algorithms For The Multiple Constant Multiplications Problem

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2009(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2009Bu tezde, birden fazla katsayının çarpımı (MCM) problemi, bir başka deyişle, bir değişkenin birden fazla katsayı ile çarpımının minimum sayıda toplama/çıkarma işlemi kullanılarak gerçeklenmesi için tasarlanmış kesin ve yaklaşık algoritmalar sunulmaktadır. Bir kesin alt ifade eliminasyonu (CSE) algoritmasının tasarımında, MCM problemini bir 0-1 tamsayı lineer programlama problemi olarak modelleyen daha önceden önerilmiş bir algoritma temel alınmıştır. Kesin CSE algoritması içinde, alan ve gecikme ölçütlerini ele alabilmek için yeni bir kesin model önerilmektedir. Kesin CSE algoritması tarafından taranacak arama uzayını küçültmek için problem indirgeme ve model basitleştirme teknikleri sunulmaktadır. Bu tekniklerin kullanımının kesin CSE algoritmasının daha büyük örnekler üzerinde uygulanmasına olanak sağladığı gösterilmektedir. Ayrıca, bu teknikler ile donatılmış kesin CSE algoritması, katsayıları genel sayı gösteriminde ele alacak ve kesin CSE algoritmasından daha iyi sonuçlar elde edecek şekilde genişletilmektedir. Bunların yanında, gerçek boyutlu örnekler üzerinde uygulanabilen bir kesin graf tabanlı algoritma sunulmaktadır. Bu kesin algoritmalara ek olarak, minimum sonuçlara oldukça yakın çözümler bulabilen ve kesin algoritmaların ele almakta zorlandığı örneklere uygulanabilen yaklaşık CSE ve graf tabanlı algoritmalar verilmektedir. Bu tezde önerilen kesin ve yaklaşık algoritmaların daha önceden önerilmiş sezgisel yöntemlerden daha iyi sonuçlar verdiği gösterilmektedir. Bunların yanısıra, bu tezde, kesin CSE algoritması gecikme kısıtı altında alanın minimize edilmesi, kapı seviyesinde alanın minimize edilmesi ve yüksek hızlı sayısal sonlu impuls cevaplı filtrelerin tasarımında alanın optimize edilmesi problemlerine uygulanmaktadır.In this thesis, exact and approximate algorithms designed for the multiple constant multiplications (MCM) problem, i.e., the implementation of the multiplication of a variable with multiple constants using minimum number of addition/subtraction operations, are introduced. In the design of an exact common subexpression elimination (CSE) algorithm, we relied on the previously proposed algorithm that models the MCM problem as a 0-1 integer linear programming problem. To handle the area and delay parameters in the exact CSE algorithm, a new exact model is proposed. To reduce the search space to be explored by the exact algorithm, problem reduction and model simplification techniques are introduced. It is shown that the use of these techniques enable the exact CSE algorithm to be applied on larger size instances. Also, the exact CSE algorithm equipped with these techniques is extended to handle the constants under general number representation yielding better solutions than those of the exact CSE algorithm. Besides, an exact graph-based algorithm that can be applied on real size instances is introduced. In addition to the exact algorithms, approximate CSE and graph-based algorithms that find similar results with the minimum solutions and can be applied on instances that the exact algorithms cannot deal with are presented. It is shown that the exact and approximate algorithms proposed in this thesis give better solutions than those of the previously proposed heuristic algorithms. Furthermore, in this thesis, the exact CSE algorithm is applied on the minimization of area under a delay constraint, the minimization of area at gate-level, and the optimization of area in high-speed digital finite impulse response filters synthesis problems.DoktoraPh

Some Optimizations of Hardware Multiplication by Constant Matrices

International audienceThis paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved

New method to design multiplier-less pulse shaping filters with minimal number of operations

Software-Defined Radio (SDR) technology is evolving rapidly, offering higher flexibility for wireless communication networks. For the sake of performance, and power consumption, filtering is commonly implemented in hardware using FPGAs. Pulse shaping in the transmitter and the corresponding matched filtering in the receiver, which together satisfy the Nyquist inter symbol interference (ISI) criterion, are no exception to this. To decrease the FPGA resources used by filters, to increase speed and to decrease power consumption the filter coefficients can be optimized by expressing them in canonical signed digit (CSD) form, using as few arithmetic operations per filter as possible, while maintaining acceptable filter characteristics. In this paper a new method to decrease the number of nonzero signed digits is presented. With this method a reduction of up to 65% of the nonzero signed digits per filter is realized, while decreasing the ISI ratio too

Synthesis of reconfigurable multiplier blocks: part I: fundamentals

Reconfigurable Multiplier Blocks (ReMB) offer significant area, delay and possibly power reduction in time multiplexed implementation of multiple constant multiplications. This paper and its companion paper (subtitled Part II- Algorithm) together present a systematic synthesis method for Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) ReMB designs. This paper presents the necessary foundation and terminology needed for developing a systematic synthesis technique. The companion paper illustrates the synthesis method through examples. The method proposed achieves reduced logic-depth and area over standard multipliers / multiplier blocks

Minimizing Design Costs of an FIR Filter Using a Novel Coefficient Optimization Algorithm

This work presents a novel coefficient optimization algorithm to reduce the area and improve the performance of finite impulse response (FIR) filter designs. Two basic architectures are commonly used in filters—direct and transposed. The coefficients of a filter can be encoded in the fewest possible nonzero bits using canonic signed digit (CSD) expressions. The proposed optimization algorithm can share common subexpressions (CS) and reduce the number of replicate operations that involve the CSD coefficients of filters with a transposed architecture. The effectiveness of the algorithm is confirmed by using filters with the collision detection multiple access (CDMA) standard, the 121-tap high-pass band, and 105- and 325-tap low-pass bands as benchmarks. For example, the proposed algorithm used in the optimization of 105-tap filter has a 30.44% smaller combinational logic area and a 16.69% better throughput/area than those of the best design that has been developed to date. Experimental results reveal that the proposed algorithm outperforms earlier designs