Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

This chapter explores different analog-to-digital conversion techniques that are suitable to be implemented in cognitive radio receivers. This chapter details the fundamentals, advantages, and drawbacks of three promising techniques: subsampling, interleaving, and compressive sensing. Due to their major maturity, subsampling- and interleaving-based systems are described in further detail, whereas compressive sensing-based systems are described as a complement of the previous techniques for underutilized spectrum applications. The feasibility of these techniques as part of software-defined radio, multistandard, and spectrum sensing receivers is demonstrated by proposing different architectures with reduced complexity at circuit level, depending on the application requirements. Additionally, the chapter proposes different solutions to integrate the advantages of these techniques in a unique analog-to-digital conversion process

Time-Interleaved Analog-to-Digital-Converters: Modeling, Blind Identification and Digital Correction of Frequency Response Mismatches

Analog-to-digital-conversion enables utilization of digital signal processing (DSP) in many applications today such as wireless communication, radar and electronic warfare. DSP is the favored choice for processing information over analog signal processing (ASP) because it can typically offer more flexibility, computational power, reproducibility, speed and accuracy when processing and extracting information. Software defined radio (SDR) receiver is one clear example of this, where radio frequency waveforms are converted into digital form as close to the antenna as possible and all the processing of the information contained in the received signal is extracted in a configurable manner using DSP. In order to achieve such goals, the information collected from the real world signals, which are commonly analog in their nature, must be converted into digital form before it can be processed using DSP in the respective systems. The common trend in these systems is to not only process ever larger bandwidths of data but also to process data in digital format at ever higher processing speeds with sufficient conversion accuracy. So the analog-to-digital-converter (ADC), which converts real world analog waveforms into digital form, is one of the most important cornerstones in these systems.The ADC must perform data conversion at higher and higher rates and digitize ever-increasing bandwidths of data. In accordance with the Nyquist-Shannon theorem, the conversion rate of the ADC must be suffcient to accomodate the BW of the signal to be digitized, in order to avoid aliasing. The conversion rate of the ADC can in general be increased by using parallel ADCs with each ADC performing the sampling at mutually different points in time. Interleaving the outputs of each of the individual ADCs provides then a higher digitization output rate. Such ADCs are referred to as TI-ADC. However, the mismatches between the ADCs cause unwanted spurious artifacts in the TI-ADC’s spectrum, ultimately leading to a loss in accuracy in the TI-ADC compared to the individual ADCs. Therefore, the removal or correction of these unwanted spurious artifacts is essential in having a high performance TI-ADC system.In order to remove the unwanted interleaving artifacts, a model that describes the behavior of the spurious distortion products is of the utmost importance as it can then facilitate the development of efficient digital post-processing schemes. One major contribution of this thesis consists of the novel and comprehensive modeling of the spurious interleaving mismatches in different TI-ADC scenarios. This novel and comprehensive modeling is then utilized in developing digital estimation and correction methods to remove the mismatch induced spurious artifacts in the TI-ADC’s spectrum and recovering its lost accuracy. Novel and first of its kind digital estimation and correction methods are developed and tested to suppress the frequency dependent mismatch spurs found in the TI-ADCs. The developed methods, in terms of the estimation of the unknown mismatches, build on statistical I/Q signal processing principles, applicable without specifically tailored calibration signals or waveforms. Techniques to increase the analog BW of the ADC are also analyzed and novel solutions are presented. The interesting combination of utilizing I/Q downconversion in conjunction with TI-ADC is examined, which not only extends the TI-ADC’s analog BW but also provides flexibility in accessing the radio spectrum. Unwanted spurious components created during the ADC’s bandwidth extension process are also analyzed and digital correction methods are developed to remove these spurs from the spectrum. The developed correction techniques for the removal of the undesired interleaving mismatch artifacts are validated and tested using various HW platforms, with up to 1 GHz instantaneous bandwidth. Comprehensive test scenarios are created using measurement data obtained from HW platforms, which are used to test and evaluate the performance of the developed interleaving mismatch estimation and correction schemes, evidencing excellent performance in all studied scenarios. The findings and results presented in this thesis contribute towards increasing the analog BW and conversion rate of ADC systems without losing conversion accuracy. Overall, these developments pave the way towards fulfilling the ever growing demands on the ADCs in terms of higher conversion BW, accuracy and speed

Pilot-Based TI-ADC Mismatch Error Calibration for IR-UWB Receivers

4openopenSchmidt C.A.; Figueroa J.L.; Cousseau J.E.; Tonello A.M.Schmidt, C. A.; Figueroa, J. L.; Cousseau, J. E.; Tonello, A. M

Pilot-Based TI-ADC Mismatch Error Calibration for IR-UWB Receivers

In this work, we rst provide an overviewof the state of the art in mismatch error estimation and correction for time-interleaved analog to digital converters (TI-ADCs). Then, we present a novel pilot-based on-line adaptive timing mismatch error estimation approach for TI-ADCs in the context of an impulse radio ultra wideband (IR-UWB) receiver with correlation-based detection. We introduce the developed method and derive the expressions for both additive white Gaussian noise (AWGN) and Rayleigh multipath fading (RMPF) channels. We also derive a lower bound on the required ADC resolution to attain a certainestimation precision. Simulations show the effectiveness of the technique when combined with an adequate compensator. We analyze the estimation error behavior as a function of signal to noise ratio (SNR) and investigate the ADC performance before and after compensation. While all mismatches combined cause the effective number of bits (ENOB) to drop to 3 bits and to 6 bits when considering only timing mismatch, estimation and correction of these errors with the proposed technique can restore a close to ideal behavior.We also show the performance loss at the receiver in terms of bit error rate (BER) and how compensation is able to signicantly improve performance.Fil: Schmidt, Christian Andrés. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Figueroa, Jose Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Cousseau, Juan Edmundo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Lopez Tonellotto, Mariana Andrea. University Of Klagenfurt; Austri

An RF BIST Architecture for Output Stages of Multistandard Radios

Article accepté pour publicationInternational audienceSoftware defined radios (SDR) platforms are in-creasingly complex systems which combine great flexibility and high performance. These two characteristics, together with highly integrated architectures make production test a challenging task. In this paper, we introduce an Radio Frequency (RF) Built-in Self-Test (BIST) strategy based on Periodically Nonuniform Sampling of the signal at the output stages of multistandard radios. We leverage the I/Q ADC channels and the DSP resources to extract the bandpass waveform at the output of the power amplifier (PA). Analytical expressions and simulations show that our time-interleaved conversion scheme is sensitive to time-skew. We show a time-skew estimation technique that allows us to surmount this obstacle. Simulation results show that we can effectively reconstruct the bandpass signal of the output stage using this architecture, opening the way for a complete RF BIST strategy for multistandard radios. Future developments will be focused on an efficient mapping to hardware of our new time-skew estimation for TIADC bandpass conversion

An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers

Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThe rapid growth of wireless communications and the massive use of wireless end-user equipments have created a demand for low-cost, low-power and low-area devices with tight specifications imposed by standards. The advances in CMOS technology allows, nowadays, designers to implement circuits that work at high-frequencies, thus, allowing the complete implementation of RF front ends in a single chip. In this work, a co-design strategy for the implementation of a fully integrated CMOS receiver for use in the ISM band is presented. The main focus is given to the Mixer and the ADC blocks of the presented architecture. The traditional approach used in RF design requires 50 matching buffers and networks and AC coupling capacitors between Mixer inputs and LNA and LO outputs. The codesign strategy avoids the use of DC choke inductors for Mixer biasing, because it is possible to use the DC level from the output of the LNA and the LO to provide bias to the Mixer. Moreover, since the entire circuit is in the same chip and the Mixer inputs are transistors gates, we should consider voltage instead of power and avoid the 50 matching networks. The proposed ADC architecture relies on a 4-bit flash converter. The main goals are to achieve low-power and high sampling frequency. To meet these goals, parametric amplification based on MOS varactors is applied to reduce the offset voltage of the comparators, avoiding the traditional and power-consuming approach of active pre-amplification gain stages

FPGA Implementation of Channel Mismatch Calibration in TIADCs for Signals in Any Nyquist Bands

This paper presents a fully digital background calibration technique of the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converters for the wideband bandlimited input signal at any Nyquist bands. The proposed technique does not require an additional reference channel nor a pilot input. The channel mismatch parameters are estimated based on the mismatch frequency band. The experimental results shows the efficiency of the proposed mitigation technique with the SNDR improvement of 16dB for 4-channel 60dB SNR TIADC clocked at 2.7GHz given a multi-tone input occupied at the third Nyquist band. The hardware architecture of the proposed technique is designed and validated on Altera FPGA DE4 board. The synthesized design utilizes a very little amount of the hardware resource in the FPGA chip and works correctly on a Hardware-In-the-Loop emulation framework

Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC

Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 19.27 dB and 35.2 dB, respectively. This analysis was done for an input signal frequency of 0.09fs. In the case of an input signal frequency of 0.45fs, an improvement by 33.06 dB and 43.14 dB is respectively achieved in SNDR and SFDR. In addition to the simulation, the algorithm was implemented in hardware for real-time evaluation. The low computational burden of the algorithm allowed an FPGA implementation with a low logic resource usage and a high system clock speed (926.95 MHz for four channel algorithm implementation). Thus, the proposed architecture can be used as a post-processing algorithm in host processors for data acquisition systems to improve the performance of TIADC