DIGITAL HEARING AID SIGNAL PROCESSING SYSTEM USING ANDROID PHONE

Objective: The objective of this research is to propose an Android-based digital hearing aid signal processing algorithm with following key features:(1) Regenerated audio match the patient-specific pattern of hearing loss, (2) noise reduction, and (3) provide flexibility to the users.Methods: The proposed signal processing algorithm is designed based on the specific hearing loss of the hearing disorder patient using inverse Fouriertransform; besides, noise reduction feature is included in the digital algorithm design as well. Proposed digital algorithm has been implemented intoan Android-based smartphone and its performance has been tested under real-time condition.Results: Simulation results show that the frequency response of the proposed digital hearing aid signal processing algorithm is in agreement withthe initial theoretical design that was carried out based on the hearing impaired patient’s audiogram. The proposed algorithm has been implementedin the Android-based smartphone and tested in real time. Results show that most of the patients are satisfied with the regenerated audio quality.According to patient’s comments, the regenerated audio is clear and the users are allowed to control the volume level. Besides, no obvious hearinglatency can be detected.Conclusion: Audio signals generated by the proposed digital signal processing algorithm show similar audio signal frequency response in boththeoretical design and MATLAB simulation results. The only difference between the design and simulation results is the amplification levels. Theproposed algorithm provides flexibility to the users by allowing them to choose the desired amplification level. In real-time testing, the proposedAndroid-based digital hearing aid is able to reduce noise level from the surrounding and the output processed speech match the patient-specifichearing loss

A laser Doppler velocimeter approach for near-wall three-dimensional turbulence measurements

A near-wall laser Doppler velocimeter approach is described that relies on a beam-turning probe which makes possible the direct measurement of the crossflow velocity at a grazing incident and the placement of optical components close to the flow region of interest regardless of test facility size. Other important elements of the approach are the use of digital frequency processing, an optically smooth measurement surface, and observation of the sensing volume at 90 degrees. The combination was found to dramatically reduce noise-in-signal effects caused by surface light scattering. Turbulent boundary-layer data to within 20 microns (y(sup+) approximately equal to 1) of the surface are presented which illustrate the potential of the approach

Trigger and data-acquisition techniques overview

1) Introduction : CERN Spbarp-S collider (UA1) ; Trigger and Digital Signal Processing (DSP). 2) CERN LHC Super Collider : Rate and data volume ; Data acquisition at LHC ; Front end, trigger levels (technologies, readout and computing, software)

A high performance cost-effective digital complex correlator for an X-band polarimetry survey

The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals. The update of the global sky models describing radio emissions over a very large spectral band requires high sensitivity experiments capable of observing large sky areas with long integration times. Here, we present the design of a new 10 GHz (X-band) polarimeter digital back-end to map the polarization components of the galactic synchrotron radiation field of the Northern Hemisphere sky. The design follows the digital processing trends in radio astronomy and implements a large bandwidth (1 GHz) digital complex cross-correlator to extract the Stokes parameters of the incoming synchrotron radiation field. The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. The implementation is based on the simultaneous digitized acquisition of the Cartesian components of the two linear receiver polarization channels. The design strategy involves a double data rate acquisition of the ADC interleaved parallel bus, and field programmable gate array device programming at the register transfer mode. The digital core of the back-end is capable of processing 32 Gbps and is built around an Altera field programmable gate array clocked at 250 MHz, 1 GSps analog to digital converters and a clock generator. The control of the field programmable gate array internal signal delays and a convenient use of its phase locked loops provide the timing requirements to achieve the target bandwidths and sensitivity. This solution is convenient for radio astronomy experiments requiring large bandwidth, high functionality, high volume availability and low cost. Of particular interest, this correlator was developed for the Galactic Emission Mapping project and is suitable for large sky area polarization continuum surveys. The solutions may also be adapted to be used at signal processing subsystem levels for large projects like the square kilometer array testbeds

Stochastic Digital Measurement Method and Its Application in Signal Processing

Classical measurement approach is often described as a process of discretizing an analogue signal in order to easily process it in some type of digital signal processor. Although this approach has been considered to be universally applicable, practical experience has shown that some signals (e.g. fast and/or noisy signals) cannot be always precisely measured. To overcome this problem, in the late 1990s, a new measurement approach called stochastic digital measurement method (SDMM) was presented. At the beginning, this method was intended for high-precision measurements of the integral (the mean value) of a product of two signals. However, in the late 2000s, it was shown that SDMM can be used to compute the Discrete Fourier Transform (DFT). Compared to the classical DFT/FFT processors, SDMM-based ones have two important advantages: first, they are much simpler and cheaper to implement, and second, they allow us to compute individual DFT components either in isolation or in parallel. This chapter is a review of the evolution of SDMM with a special emphasis on a two-bit SDMM. Topics covered include: theoretical foundations of SDMM, the architecture of SDMM-DFT processor and an example of prototype instrument used in power grid networks.This is the peer-reviewed version of the chapter: Radonjić, A., Sovilj, P., Đorđević Kozarov, J., Vujičić, V., 2019. Stochastic Digital Measurement Method and Its Application in Signal Processing, in: Advances in Engineering Research. Volume 27. Nova Science Publishers, Hauppauge, pp. 169–190. ISBN 978-1-5361-4803-

Linear and nonlinear adaptive digital filters and their applications.

Adaptive digital signal processing has matured to the point where it now constitutes an important part of statistical signal processing. However, high speed adaptive digital filtering and nonlinear adaptive digital filtering are yet to be developed. In this dissertation, a family of high speed linear adaptive digital filters, which are suitable for parallel realization, are first presented. They are (1) Delayed N-path adaptive finite impulse response (DNA-FIR) digital filters; (2) Delayed N-path adaptive linear phase finite impulse response (DNALP-FIR) digital filters; (3) Delayed N-path equation-error based adaptive infinite impulse response (DNEEBA-IIR) digital filters. By using multiple digital signal processors in parallel, the processing speed of this type of filters can be increased compared with the conventional realizations. They are contrived to be useful for general applications in adaptive digital signal processing. Comparison studies have been conducted among the proposed DNA-FIR digital filter, the block implementation of adaptive finite impulse response (BIA-FIR) digital filter, and the conventional adaptive finite impulse response (CA-FIR) digital filter. It has been shown that the processing speed of the proposed DNA-FIR digital filter is N times that of the BIA-FIR digital filter (given block length N and time domain realization). Then a nonlinear delayed N-path adaptive finite impulse response (NDNA-FIR) digital filter is developed, the parallel structure of which lends itself to high speed implementation. This NDNA-FIR digital filter compares favorably with the CA-FIR digital filter and the nonlinear median filter when applied to broadband noise cancellation. The last part of this dissertation describes the structure and its adaptive algorithm of a nonlinear adaptive infinite impulse response (IIR) digital filter. This IIR digital filter is bounded input bounded output (BIBO) stable. Based on this structure, an individual adaptation scheme is incorporated into the adaptive algorithm to improve the convergence speed.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1994 .L515. Source: Dissertation Abstracts International, Volume: 56-01, Section: B, page: 0427. Adviser: Hon Keung Kwan. Thesis (Ph.D.)--University of Windsor (Canada), 1994

A REAL TIME GENERAL PURPOSE SIGNAL PROCESSOR ARCHITECTURE.

Digital signal processing has many applications in the areas of signal, radar, speech and image processing and real time implementation requires a very high throughput rate. Various processor architectures have been investigated 1-6 which reveals that a special purpose processor appropriate to the algorithms should be designed in order to achieve high throughput rates. Recently research efforts 7-14 are directed towards the exploitation of parallelism in the algorithms and parallel computation of these algorithms. The objective of this work is to propose new concepts for high speed computation of real time general purpose signal processing algorithms. A novel architecture of a real time general purpose data flow signal processor (DFSP), based on the binary tree structure, is proposed for real time signal processing applications. The data flow signal processor exploits distributed, parallel, and pipeline processing approaches to achieve high throughput rates. The processor utilizes the residue number system (RNS) for high speed signal processing applications. The arithmetic operations in RNS can be performed via Random Access Memory (RAM) look up tables, and the execution time of any particular arithmetic operation is reduced to the access time of a RAM. The data flow signal processor is demonstrated to be suitable for performing recursive, non-recursive digital filtering and convolution operations. Finally the thesis describes various alternatives for programming the DFSP, and an interactive program environment is used to write application programs without knowing the internal architecture of the DFSP.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1985 .J353. Source: Dissertation Abstracts International, Volume: 46-02, Section: B, page: 0601. Thesis (Ph.D.)--University of Windsor (Canada), 1985