A system for calculating the greatest common denominator implemented using asynchrobatic logic

An asynchrobatic system that uses Euclid's algorithm to calculate the greatest common denominator of two numbers is presented. This algorithm is a simple system that contains both repetition and decision, and therefore demonstrates that asynchrobatic logic can be used to implement arbitrarily complex computational systems. Under typical conditions on a 0.35 mum process, a 16-bit implementation can perform a 24-cycle test vector in 2.067 mus with a power consumption of 3.257 nW

An asynchrobatic, radix-four, carry look-ahead adder

A low-power, Asynchrobatic (asynchronous, quasi-adiabatic), sixteen-bit, radix-four, parallel-prefix adder circuit is presented. The results show that it is an efficient, low power design, and that as would be expected with an asynchronous design, its performance is determined by its operating conditions. On a 0.35 mum CMOS process, under ldquotypicalrdquo process conditions, operating at an effective frequency of 22 MHz, an addition can be performed using 69 pW, with 48.3 pW used by the control logic and 20.7 pW by the data-path

Design of a Quasi-Adiabatic Current-Mode Neurostimulator Integrated Circuit for Deep Brain Stimulation

Electrical stimulation of neural tissues is a valuable tool in the retinal prosthesis, cardiac pacemakers, and Deep Brain Stimulation (DBS). DBS is being to treat a growing number of neurological disorders, such as movement disorder, epilepsy, and Parkinson’s disease. The role of the electronic stimulator is paramount in such application, and significant design challenges are to be met to enhance safety and reliability. A current-source based stimulator can accurately deliver a charge-balanced stimulus maintaining patient safety. In this thesis, a general-purpose current-mode neurostimulator (CMS) based upon a new quasi-adiabatic driving technique is proposed which can theoretically achieve more than 80% efficiency with the help of a dynamic high voltage supply (DHVS) as opposed to most conventional general-purpose CMS having less than 25% efficiency. The high-voltage supply is required to withstand the voltage seen across the electrodes (>10V) due to the time-varying impedance presented by the electrode-tissue interface. The overall efficiency of the designed CMS is limited by the efficiency of the DHVS. A HVDD of 15V is created by the DHVS from an input voltage (VDD) of 3V. The DHVS circuit is made by cascading five charge pump circuits using the AMI 0.5µm CMOS process. It can maintain more than 60% efficiency for a wide range of load current from 25µA to 1.4mA, with peak efficiency at 67% and this is comparable with existing specific-purpose state-of-the-art high-voltage supplies used in a current stimulator. The stimulator designed in this thesis employs a new efficient charge recycling mechanism to enhance the overall efficiency, compared to the existing state-of-the-art CMSs. Thus, the overall CMS efficiency is improved by 20% to 25%. A current source, programmable by 8-bit digital input, is also designed which has an output impedance greater than 2MΩ with a dropout voltage of only 120mV. Measurements show voltage compliance exceeding +/-15V when driving a biphasic current stimulus of 10µA to 2.5mA through a simplified R-C model of the electrode-tissue interface. The voltage compliance is defined as the maximum voltage a stimulator can apply across the electrodes to achieve neural stimulation

High-speed low-power modulator driver arrays for medium-reach optical networks

The internet is becoming the ubiquitous tool that is changing the lives of so many citizens across the world. Commerce, government, industry, healthcare and social interactions are all increasingly using internet applications to improve and facilitate communications. This is especially true for videoenabled applications, which currently demand much higher data rates and quality from data networks. High definition TV streaming services are emerging and these again will significantly push the demand for widely deployed, high-bandwidth services. The current access passive optical networks (PONs) use a single wavelength for downstream transmission and a separate one for upstream transmission. Incorporating wavelength-division multiplexing (WDM) in a PON allows for much higher bandwidths in both directions. While WDM technologies have been successfully deployed for many years in metro and core networks, in access networks they are not commonly used yet. This is mainly due to the high costs associated with deploying entire WDM access networks. However, the present optical networks cannot be simply and cost-effectively scaled to provide the capacity for tomorrow’s users. As an effect there is a strong need for new WDM access components which are compact, cost-competitive and mass-manufacturable. Increasing the number of wavelengths for WDM-PON automatically leads to an increase in the number of single pluggable transceivers, which brings substantial design challenges and additional costs. The multitude of TXs and RXs for different wavelength channels increases the total footprint considerably. Photonic integration of transceivers into arrays will significantly reduce the footprint and cost. However, the total power consumption of an array device is an issue. To avoid the use of a thermoelectric cooler, the integration density of components is severely limited by the heat dissipating capabilities offered by their package. As a result the WDM-PON philosophy necessitates the reduction of the transceiver’s power dissipation. From this plea it is apparent that the main technology challenges for realizing future-proof optical (access) networks are reducing active component power consumption, shrinking form factors and lowering assembly costs. In this perspective an over 100 Gb/s throughput component, composed of 10 channels at 11.3 Gb/s per wavelength channel would be a great contribution to the expansion of customer bandwidth. It can provide increased line rates to the end users at speeds of 10 Gb/s per wavelength. As RXs typically consume much less power than externally modulated TXs, they can relatively easily be integrated into an array. Mainly high speed optical transmitters have significant power consumptions and the heat generation caused by power dissipation forms a critical obstacle in the development of a 10-channel transmitter, which again underlines the importance of power reduction. Alongside the introduction of WDM in access networks, also inter-office point-to-point connections in data center environments could benefit from the WDM philosophy. As data center operators often suffer from fiber scarcity or do not own their fiber infrastructure, WDM technologies are essential to deliver reach and capacity extension for these scenarios. Interdata center communication also benefits from cost-, footprint- and energyefficient components operating at high speed to maximize the throughput. As an effect integrated over 100 Gb/s transceivers, such as 4 channels at 28 Gb/s, are highly desirable. The research described in this dissertation was partly funded by the European FP7 ICT project C3PO (Colourless and Coolerless Components for low Power Optical Networks) and the UGent special research fund. The C3PO project aimed to develop a new generation of green Si-photonic compatible components with record low power consumption, that can enable bandwidth growth and constrain the total cost. C3PO envisioned building high-capacity access networks employing reflective photonic components. To achieve this, cost-competitive reflective transmitters based on electroabsorption modulators (EAM) needed to be closely integrated into arrays. A multi-wavelength optical source provides the required wavelength channels for both downstream and upstream signals in the WDM-PON. Chapter 1 gives a short overview of a PON and describes the main implementations of a WDM-PON access network. It introduces integrated low power transmitter arrays for a cost-effective architecture of WDM-PONs and inter-data center communication. Chapter 2 compares different optical transmitters and gives a short overview of their most important characteristics. External modulation through both Mach-Zehnder modulators (MZMs) and EAMs is described. It shows that EAMs are the best choice for low power transmitter array integration, thanks to their lower drive voltage and smaller form factor, compared to MZMs. To achieve a reduced consumption, the electronic modulator driver topology is studied in chapter 3. The challenge in designing modulator drivers is the need to deliver very large currents in combination with high voltage swings. Four distinct output configurations are compared and techniques to reduce the power consumption of the drivers are described. Chapter 5 presents duobinary (DB), a modulation scheme that is gaining interest in today’s optical transmission. As the required bandwidth is about half that of NRZ, it softens the constraints on the transmitter bandwidth. Thanks to its narrow optical spectrum, it has an improved tolerance to dispersion in long haul single mode links and it can improve the spectral efficiency in WDM architectures. For optical DB a precoder is necessary to assure the received signal is equal to the original binary signal. The conducted research that resulted in this dissertation produced 2 low power EAM driver arrays: A 10-channel 113 Gb/s modulator driver array with state-of-the art ultra-low power consumption. A 2-channel 56 Gb/s duobinary driver array with a differential output with low power consumption. Both designs are elaborately analyzed in chapter 4 and 6 respectively. To the best of our knowledge the 10-channel EAM driver array is the first in its kind, while achieving the lowest power consumption for an EAM driver so far reported, 50% below the state of the art in power consumption. The 2-channel EAM driver array is the fastest modulator driver including on-chip duobinary encoding and precoding reported so far. The final chapter provides an overview of the foremost conclusions from the presented research. It is concluded with suggestions for further research

Adiabatic Approach for Low-Power Passive Near Field Communication Systems

This thesis tackles the need of ultra-low power electronics in the power limited passive Near Field Communication (NFC) systems. One of the techniques that has proven the potential of delivering low power operation is the Adiabatic Logic Technique. However, the low power benefits of the adiabatic circuits come with the challenges due to the absence of single opinion on the most energy efficient adiabatic logic family which constitute appropriate trade-offs between computation time, area and complexity based on the circuit and the power-clocking schemes. Therefore, five energy efficient adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking schemes were chosen. Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of the multi-phase adiabatic families was evaluated and compared based on the design examples such as 2-bit ring counter, 3-bit Up-Down counter and 16-bit Cyclic Redundancy Check (CRC) circuit (benchmark circuit) based on ISO 14443-3A standard. Several trade-offs, design rules, and an appropriate range for the supply voltage scaling for multi-phase adiabatic logic are proposed. Furthermore, based on the NFC standard (ISO 14443-3A), data is frequently encoded using Manchester coding technique before transmitting it to the reader. Therefore, if Manchester encoding can be implemented using adiabatic logic technique, energy benefits are expected. However, adiabatic implementation of Manchester encoding presents a challenge. Therefore, a novel method for implementing Manchester encoding using adiabatic logic is proposed overcoming the challenges arising due to the AC power-clock. Other challenges that come with the dynamic nature of the adiabatic gates and the complexity of the 4-phase power-clocking scheme is in synchronizing the power-clock v phases and the time spent in designing, validation and debugging of errors. This requires a specific modelling approach to describe the adiabatic logic behaviour at the higher level of abstraction. However, describing adiabatic logic behaviour using Hardware Description Languages (HDLs) is a challenging problem due to the requirement of modelling the AC power-clock and the dual-rail inputs and outputs. Therefore, a VHDL-based modelling approach for the 4-phase adiabatic logic technique is developed for functional simulation, precise timing analysis and as an improvement over the previously described approaches

Asynchrobatic logic for low-power VLSI design

In this work, Asynchrobatic Logic is presented. It is a novel low-power design style that combines the energy saving benefits of asynchronous logic and adiabatic logic to produce systems whose power dissipation is reduced in several different ways. The term “Asynchrobatic” is a new word that can be used to describe these types of systems, and is derived from the concatenation and shortening of Asynchronous, Adiabatic Logic. This thesis introduces the concept and theory behind Asynchrobatic Logic. It first provides an introductory background to both underlying parent technologies (asynchronous logic and adiabatic logic). The background material continues with an explanation of a number of possible methods for designing complex data-path cells used in the adiabatic data-path. Asynchrobatic Logic is then introduced as a comparison between asynchronous and Asynchrobatic buffer chains, showing that for wide systems, it operates more efficiently. Two more-complex sub-systems are presented, firstly a layout implementation of the substitution boxes from the Twofish encryption algorithm, and secondly a front-end only (without parasitic capacitances, resistances) simulation that demonstrates a functional system capable of calculating the Greatest Common Denominator (GCD) of a pair of 16-bit unsigned integers, which under typical conditions on a 0.35μm process, executed a test vector requiring twenty-four iterations in 2.067μs with a power consumption of 3.257nW. These examples show that the concept of Asynchrobatic Logic has the potential to be used in real-world applications, and is not just theory without application. At the time of its first publication in 2004, Asynchrobatic Logic was both unique and ground-breaking, as this was the first time that consideration had been given to operating large-scale adiabatic logic in an asynchronous fashion, and the first time that Asynchronous Stepwise Charging (ASWC) had been used to drive an adiabatic data-path

IDPAL - Input Decoupled Partially Adiabatic Logic Family: Theory and Implementation of Side-Channel Attack Resistant Circuits

The Input Decoupled Partially Adiabatic Logic (IDPAL) family was developed by Cutitaru to consume less power than other logic families as well as producing a resistance to side-channel attacks. With modifications made to IDPAL, the side-channel attack resistance is being revisited and quantified. The three logic families are compared in the work are CMOS, 2N2P, and IDPAL. An AND/NAND gate was created using each logic family and compared with two tests: 1) a simulated side-channel attack and 2) an energy analysis. In this work, a side-channel attack is the ability to predict the inputs of a logic circuit based on the electrical current waveform. For the Test 1, a higher prediction error suggests a higher resistance to attack. IDPAL produced the highest error in this test at 50.000%, which is 40.625% higher than in CMOS and 28.125% higher than in 2N2P. In Test 2, two primary statistics that were observed the variance in current trace (NSD and NED). Lower values of these measures implies a higher chance of a model resisting a side-channel attack. For the individual logic gates, the IDPAL model showed a lower variance in one of the two measures. For the Kogge-Stone adder, a more complex circuit, the IDPAL model was superior in both tests. With the results of the small and larger scale experiments in agreement, the final conclusion is that IDPAL does, indeed, resist side-channel attacks in a stronger fashion than other logic families