Self-healing concepts involving fine-grained redundancy for electronic systems

The start of the digital revolution came through the metal-oxide-semiconductor field-effect transistor (MOSFET) in 1959 followed by massive integration onto a silicon die by means of constant down scaling of individual components. Digital systems for certain applications require fault-tolerance against faults caused by temporary or permanent influence. The most widely used technique is triple module redundancy (TMR) in conjunction with a majority voter, which is regarded as a passive fault mitigation strategy. Design by functional resilience has been applied to circuit structures for increased fault-tolerance and towards self-diagnostic triggered self-healing. The focus of this thesis is therefore to develop new design strategies for fault detection and mitigation within transistor, gate and cell design levels. The research described in this thesis makes three contributions. The first contribution is based on adding fine-grained transistor level redundancy to logic gates in order to accomplish stuck-at fault-tolerance. The objective is to realise maximum fault-masking for a logic gate with minimal added redundant transistors. In the case of non-maskable stuck-at faults, the gate structure generates an intrinsic indication signal that is suitable for autonomous self-healing functions. As a result, logic circuitry utilising this design is now able to differentiate between gate faults and faults occurring in inter-gate connections. This distinction between fault-types can then be used for triggering selective self-healing responses. The second contribution is a logic matrix element which applies the three core redundancy concepts of spatial- temporal- and data-redundancy. This logic structure is composed of quad-modular redundant structures and is capable of selective fault-masking and localisation depending of fault-type at the cell level, which is referred to as a spatiotemporal quadded logic cell (QLC) structure. This QLC structure has the capability of cellular self-healing. Through the combination of fault-tolerant and masking logic features the QLC is designed with a fault-behaviour that is equal to existing quadded logic designs using only 33.3% of the equivalent transistor resources. The inherent self-diagnosing feature of QLC is capable of identifying individual faulty cells and can trigger self-healing features. The final contribution is focused on the conversion of finite state machines (FSM) into memory to achieve better state transition timing, minimal memory utilisation and fault protection compared to common FSM designs. A novel implementation based on content-addressable type memory (CAM) is used to achieve this. The FSM is further enhanced by creating the design out of logic gates of the first contribution by achieving stuck-at fault resilience. Applying cross-data parity checking, the FSM becomes equipped with single bit fault detection and correction

Integrated Synthesis Methodology for Crossbar Arrays

Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178, and supported by the TUBITAK-Career project #113E76

Permanent and transient fault tolerance for reconfigurable nano-crossbar arrays

This paper studies fault tolerance in switching reconfigurable nano-crossbar arrays. Both permanent and transient faults are taken into account by independently assigning stuck-open and stuck-closed fault probabilities into crosspoints. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. The algorithm's effectiveness is demonstrated on standard benchmark circuits in terms of runtime, success rate, and accuracy. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions. In this way, we are able to specify fault tolerance performances of nano-crossbars without relying on randomly generated faults that is relatively costly regarding that the number of fault distributions in a crossbar grows exponentially with the crossbar size.Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer project is supported by the EU-H2020-RISE project NANOxCOMP 691178 and the TUBITAK-CAREER project 113E760.Accepted for publicatio

Permanent and transient fault tolerance for reconfigurable nano-crossbar arrays

This paper studies fault tolerance in switching reconfigurable nano-crossbar arrays. Both permanent and transient faults are taken into account by independently assigning stuck-open and stuck-closed fault probabilities into crosspoints. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. The algorithm's effectiveness is demonstrated on standard benchmark circuits in terms of runtime, success rate, and accuracy. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions. In this way, we are able to specify fault tolerance performances of nano-crossbars without relying on randomly generated faults that is relatively costly regarding that the number of fault distributions in a crossbar grows exponentially with the crossbar size.Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer project is supported by the EU-H2020-RISE project NANOxCOMP 691178 and the TUBITAK-CAREER project 113E760.Accepted for publicatio

Thermal profiling in CMOS/memristor hybrid architectures

CMOS/memristor hybrid architectures combine conventional CMOS processing elements with thin-film memristor-based crossbar circuits for high-density reconfigurable systems. These architectures have received an explosive growth in research over the past few years due to the first practical demonstration of a thin-film memristor in 2008. The reliability and lifetimes of both the CMOS and memristor partitions of these architectures are severely affected by temperature variations across the chip. Therefore, it is expected that dynamic thermal management (DTM) mechanisms will be needed to improve their reliability and lifetime. This thesis explores one aspect of DTM--thermal profiling--in a CMOS/memristor memory architecture. A temperature sensing resistive random access memory (TSRRAM) was designed. Temperature information is extracted from the TSRRAM by measuring the write time of thin-film memristors. Active and passive sensing mechanisms are also introduced as means for DTM algorithms to determine the thermal profile of the chip. Crosstherm, a simulation framework, was developed to analyze the effects of temperature variations in CMOS/memristor architectures. The TSRRAM design was simulated using the Crosstherm framework for four CMOS processor benchmarks. Passive sensing produced a mean absolute sensor error across all benchmarks of 2.14 K. The size of the DTM unit\u27s memory was also shown to have a significant impact on the accuracy of extracted thermal data during passive sensing. Active sensing was also demonstrated to show the effect of dynamic adjustment of sensor resolution on the accuracy of hotspot temperature estimations

ARTI-based holonic control implementation for a manufacturing system using the base architecture

Thesis (MEng)--Stellenbosch University, 2022.ENGLISH SUMMARY: With industry’s drive to adopt Industry 4.0 technologies, and their enabling technologies, in manufacturing processes, intelligent automated manufacturing has become largely sought after. With defining features such as robustness, reconfigurability and scalability, the Holonic Manufacturing Execution System (HMES) approach shows great potential to satisfy Industry 4.0 requirements. Implementations of these systems have been historically known to require great development effort and time. These implementations are however being aided by the development of holonic reference architectures, such as the Product-Resource-Order-Staff-Architecture (PROSA) and its recent revision the Activity-Resource- Type-Instance (ARTI) architecture. This thesis presents an ARTI-based HMES implementation. The implementation of this system is aided through the use of the Biography-Attributes-Schedule-Execution (BASE) architecture for digital administration shells. The BASE architecture was initially developed as a framework for the development of a digital administration shell for a human worker, in order to elevate the human worker to the level of a Cyber-Physical System. It was however proposed that the BASE architecture also had the potential to be used in a manufacturing context. The possibility of implementing the ARTI-based HMES using the BASE architecture for the respective ARTI holons is confirmed through a mapping of the ARTI architecture to the BASE architecture. The HMES is implemented on a Fischertechnik Industry 4.0 Training Factory, a small-scale manufacturing system, as a case study system. The complexity of the case study, which comprises several interacting subsystems, provides a good basis for evaluating the ARTI and BASE architectures for HMES development. The thesis concludes that the ARTI architecture provides a well-defined structure for the conceptual design of HMESs, while the BASE architecture effectively supports the implementation of ARTI-based HMESs with little additional development required.AFRIKAANS OPSOMMING: Met die industrie se strewe om Industrie 4.0-tegnologieë, en hul bemagtigende tegnologieë, in vervaardigingsprosesse aan te neem, het intelligente geoutomatiseerde vervaardiging grootliks gesog geword. Met kenmerke soos robuustheid, herkonfigureerbaarheid en skaleerbaarheid, toon die Holonic Manufacturing Execution System (HMES) benadering groot potensiaal om aan Industrie 4.0 vereistes te voldoen. Dit is histories bekend dat die implementering van hierdie stelsels groot ontwikkelingspogings en tyd verg. Hierdie implementerings word egter aangehelp deur die ontwikkeling van holoniese verwysingsargitekture, soos die Product-Resource-Order-Staff-Architecture (PROSA) en die onlangse hersiening daarvan die Activity-Resource-Type-Instance (ARTI) argitektuur. Hierdie tesis bied 'n ARTI-gebaseerde HMES-implementering aan. Die implementering van hierdie stelsel is aangehelp deur die gebruik van die Biography-Attributes-Schedule-Execution (BASE) argitektuur vir digitale administrasiedoppe. Die BASE argitektuur is aanvanklik ontwikkel as 'n raamwerk vir die ontwikkeling van 'n digitale administrasiedop vir 'n menslike werker, om die menslike werker tot die vlak van 'n Cyber-Physical System te verhef. Daar is egter voorgestel dat die BASE argitektuur ook die potensiaal het om in 'n vervaardigingskonteks gebruik te word. Die moontlikheid om die ARTI-gebaseerde HMES te implementeer deur gebruik te maak van die BASE argitektuur vir die onderskeie ARTI-holone, is bevestig deur 'n kartering van die ARTI argitektuur na die BASE argitektuur. Die HMES is geïmplementeer op 'n Fischertechnik Industry 4.0 Training Factory, 'n kleinskaalse vervaardigingstelsel, as 'n gevallestudiestelsel. Die kompleksiteit van die gevallestudie, wat verskeie interaktiewe substelsels bevat, bied 'n goeie basis vir die evaluering van die ARTI en BASE argitekture vir HMES-ontwikkeling. Die tesis bevind dat die ARTI argitektuur 'n goed-gedefinieerde struktuur vir die konseptuele ontwerp van ‘n HMES verskaf, terwyl die BASE argitektuur die implementering van ‘n ARTI-gebaseerde HMES effektief ondersteun, met min bykomende ontwikkeling wat nodig is.Master

Heterogeneous Reconfigurable Fabrics for In-circuit Training and Evaluation of Neuromorphic Architectures

A heterogeneous device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. The resulting Hybrid Spin/Charge FPGA (HSC-FPGA) using magnetic tunnel junction (MTJ) devices within this topology demonstrates commensurate reductions in area and power consumption over fabrics having LUTs constructed with either individual technology alone. Herein, a hierarchical top-down design approach is used to develop the HSCFPGA starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication paradigms. This facilitates a novel architectural approach to reduce leakage energy, minimize communication occurrence and energy cost by eliminating unnecessary data transfer, and support auto-tuning for resilience. Furthermore, HSC-FPGA enables new advantages of technology co-design which trades off alternative mappings between emerging devices and transistors at runtime by allowing dynamic remapping to adaptively leverage the intrinsic computing features of each device technology. HSC-FPGA offers a platform for fine-grained Logic-In-Memory architectures and runtime adaptive hardware. An orthogonal dimension of fabric heterogeneity is also non-determinism enabled by either low-voltage CMOS or probabilistic emerging devices. It can be realized using probabilistic devices within a reconfigurable network to blend deterministic and probabilistic computational models. Herein, consider the probabilistic spin logic p-bit device as a fabric element comprising a crossbar-structured weighted array. The Programmability of the resistive network interconnecting p-bit devices can be achieved by modifying the resistive states of the array\u27s weighted connections. Thus, the programmable weighted array forms a CLB-scale macro co-processing element with bitstream programmability. This allows field programmability for a wide range of classification problems and recognition tasks to allow fluid mappings of probabilistic and deterministic computing approaches. In particular, a Deep Belief Network (DBN) is implemented in the field using recurrent layers of co-processing elements to form an n x m1 x m2 x ::: x mi weighted array as a configurable hardware circuit with an n-input layer followed by i ≥ 1 hidden layers. As neuromorphic architectures using post-CMOS devices increase in capability and network size, the utility and benefits of reconfigurable fabrics of neuromorphic modules can be anticipated to continue to accelerate

Evolutionary algorithms for synthesis and optimisation of sequential logic circuits

Considerable progress has been made recently 1n the understanding of combinational logic optimization. Consequently a large number of university and industrial Electric Computing Aided Design (ECAD) programs are now available for optimal logic synthesis of combinational circuits. The progress with sequential logic synthesis and optimization, on the other hand, is considerably less mature. In recent years, evolutionary algorithms have been found to be remarkably effective way of using computers for solving difficult problems. This thesis is, in large part, a concentrated effort to apply this philosophy to the synthesis and optimization of sequential circuits. A state assignment based on the use of a Genetic Algorithm (GA) for the optimal synthesis of sequential circuits is presented. The state assignment determines the structure of the sequential circuit realizing the state machine and therefore its area and performances. The synthesis based on the GA approach produced designs with the smallest area to date. Test results on standard fmite state machine (FS:M) benchmarks show that the GA could generate state assignments, which required on average 15.44% fewer gates and 13.47% fewer literals compared with alternative techniques. Hardware evolution is performed through a succeSSlOn of changes/reconfigurations of elementary components, inter-connectivity and selection of the fittest configurations until the target functionality is reached. The thesis presents new approaches, which combine both genetic algorithm for state assignment and extrinsic Evolvable Hardware (EHW) to design sequential logic circuits. The implemented evolutionary algorithms are able to design logic circuits with size and complexity, which have not been demonstrated in published work. There are still plenty of opportunities to develop this new line of research for the synthesis, optimization and test of novel digital, analogue and mixed circuits. This should lead to a new generation of Electronic Design Automation tools.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Evolutionary algorithms for synthesis and optimisation of sequential logic circuits.

Considerable progress has been made recently 1n the understanding ofcombinational logic optimization. Consequently a large number of universityand industrial Electric Computing Aided Design (ECAD) programs are nowavailable for optimal logic synthesis of combinational circuits. The progresswith sequential logic synthesis and optimization, on the other hand, isconsiderably less mature.In recent years, evolutionary algorithms have been found to be remarkablyeffective way of using computers for solving difficult problems. This thesis is,in large part, a concentrated effort to apply this philosophy to the synthesisand optimization of sequential circuits.A state assignment based on the use of a Genetic Algorithm (GA) for theoptimal synthesis of sequential circuits is presented. The state assignmentdetermines the structure of the sequential circuit realizing the state machineand therefore its area and performances. The synthesis based on the GAapproach produced designs with the smallest area to date. Test results onstandard fmite state machine (FS:M) benchmarks show that the GA couldgenerate state assignments, which required on average 15.44% fewer gatesand 13.47% fewer literals compared with alternative techniques.Hardware evolution is performed through a succeSSlOn ofchanges/reconfigurations of elementary components, inter-connectivity andselection of the fittest configurations until the target functionality is reached.The thesis presents new approaches, which combine both genetic algorithmfor state assignment and extrinsic Evolvable Hardware (EHW) to designsequential logic circuits. The implemented evolutionary algorithms are able todesign logic circuits with size and complexity, which have not beendemonstrated in published work.There are still plenty of opportunities to develop this new line of research forthe synthesis, optimization and test of novel digital, analogue and mixedcircuits. This should lead to a new generation of Electronic DesignAutomation tools