More is Less, Less is More: Molecular-Scale Photonic NoC Power Topologies

Abstract Molecular-scale Network-on-Chip (mNoC) crossbars use quantum dot LEDs as an on-chip light source, and chromophores to provide optical signal filtering for receivers. An mNoC reduces power consumption or enables scaling to larger crossbars for a reduced energy budget compared to current nanophotonic NoC crossbars. Since communication latency is reduced by using a high-radix crossbar, minimizing power consumption becomes a primary design target. Conventional Single Writer Multiple Reader (SWMR) photonic crossbar designs broadcast all packets, and incur the commensurate required power, even if only two nodes are communicating. This paper introduces power topologies, enabled by unique capabilities of mNoC technology, to reduce overall interconnect power consumption. A power topology corresponds to the logical connectivity provided by a given power mode. Broadcast is one power mode and it consumes the maximum power. Additional power modes consume less power but allow a source to communicate with only a statically defined, potentially non-contiguous, subset of nodes. Overall interconnect power is reduced if the more frequently communicating nodes use modes that consume less power, while less frequently communicating nodes use modes that consume more power. We also investigate thread mapping techniques to fully exploit power topologies. We explore various mNoC power topologies with one, two and four power modes for a radix-256 SWMR mNoC crossbar. Our results show that the combination of power topologies and intelligent thread mapping can reduce total mNoC power by up Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. to 51% on average for a set of 12 SPLASH benchmarks. Furthermore performance is 10% better than conventional resonator-based photonic NoCs and energy is reduced by 72%

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Advanced Applications in Nanophotonics

Nanophotonics is a fast-growing area of both scientific significance and practical value for applications. Nanophotonics studies the interaction between light and electronic systems in nanomaterials and nanostructures as well as the behavior of light in nanometer scales. It covers many hot topics such as plasmonics, two-dimensional materials, and silicon photonics. Increasing attention is given to the area and nanophotonics is expected to have significant impact on future technology advances. This thesis work focuses on three aspects of nanophotonics. The first aspect is in exploring the nonlocal effect and surface correction for nanometer-length-scale plasmonic structures. Plasmonics is the study of the interaction between electromagnetic fields and free electrons in a metal. It exploits the unique optical properties of metallic nanostructures to enable routing and manipulation of light at the nanoscale, where nonlocal effect becomes important. Here we introduce a new surface hydrodynamic model for plasmon propagation at interfaces, which incorporates both nonlocality and surface contributions. This surface correction is calculated via a discontinuity in the normal component of the electric displacement in conjunction with Feibelman's d-parameters, thus enabling rapid numerical calculation of nanostructures without requiring a full quantum calculation because of its large computational requirement. We examine numerical calculations of surface plasmon polaritons propagation at a single interface structure, and then for a more complex thin-film structures. The second aspect is investigating the third-harmonic generation in thick multilayer graphene. Graphene is the first two-dimensional material to be discovered and has attracted much interest because of its remarkable two-dimensional electronic, optical, mechanical, and thermal properties. Multilayer graphene, can be seen as stacking of monolayer graphene, and it offers an array of properties that are of interest for optical physics and devices. We describe the layer-dependent for third-harmonic generation in thick multilayer graphene on quartz substrate. The third harmonic signal of multilayer graphene exhibits a complex dependence on its layer number showing that the optimal third harmonic signal at 24 layers, in good agreement with two theoretical models. The third aspect is an exploration in silicon photonics of design and demonstration of a differential phase shift keying demodulator based on coherent perfect absorption effect. Silicon photonics is considered a potential future communication system mainly due to its compact footprint, dense integration, and compatibility with mature silicon integrated circuit manufacturing. Differential phase shift keying based system offers advantages, e.g., dispersion tolerance, improved sensitivity, and does not require coherent detection. Coherent perfect absorption uses a ring resonator works for the critical coupling condition at resonance frequency. This work shows a new compact demodulator circuit can be integrated in all optical-system

Modern Applications in Optics and Photonics: From Sensing and Analytics to Communication

Optics and photonics are among the key technologies of the 21st century, and offer potential for novel applications in areas such as sensing and spectroscopy, analytics, monitoring, biomedical imaging/diagnostics, and optical communication technology. The high degree of control over light fields, together with the capabilities of modern processing and integration technology, enables new optical measurement systems with enhanced functionality and sensitivity. They are attractive for a range of applications that were previously inaccessible. This Special Issue aims to provide an overview of some of the most advanced application areas in optics and photonics and indicate the broad potential for the future

Pulsed dynamics in silicon and diamond photonic nanostructures

The work carried out in this thesis has been motivated by the promising applicability of photonic nanostructures in optical communications, internet data centers (ICD) and biosensing, to name a few. In particular, the dispersion and nonlinear engineering that silicon photonic crystal waveguides (Si-PhCWGs) and diamond-fin waveguides allow, can be exploited in the design of important photonic components, such as frequency comb generators, Raman amplifiers or filters. Within such objectives, we present rigorous and comprehensive theoretical models where all relevant linear and nonlinear optical effects, including modal dispersion, waveguide loss, free-carrier (FC), Kerr and Raman effects are considered. In the case of the newly developed subwavelength diamond-fin waveg- uides, we complete a detailed characterization of their dispersion and nonlinear optical properties, along with an analysis of pulsed dynamics in these structures. As a relevant application, we demonstrate how these waveguides can be employed to efficiently gener- ate soliton frequency combs in the visible spectral domain. With regards to Si-PhCWGs, we firstly explore the effect of stimulated Raman scattering in the slow-light regime, and demonstrate that signal amplification without pulse distortion can be achieved. Secondly, we add photonic crystal cavities (PhCCs) alongside the Si-PhCWG, with the associated inter-cavity coupling and waveguide-cavity interactions. Therefore, we describe a novel mathematical model and its corresponding computational tool that solves the dynamics of the forwards and backwards propagating pulses, the energy in the cavities and the FCs at the waveguide and at the cavities. Finally, we show the potential practical use of the model by simulating a photonic drop-filter with back reflection nulling

TOWARDS RELIABLE NANOPHOTONIC INTERCONNECTION NETWORK DESIGNS

As technology scales into deep submicron domains, electrical wires start to face critical challenges in latency and power since they do not scale well as compared to transistors. Many recent researches have shifted focus to optical on-chip interconnection because of its promises of high bandwidth density, low propagation delay, distance-independent power consumption (compared to metal), and natural support for multicast and broadcast. Unfortunately, while optical interconnect provides many attractive and promising features, there are also fundamental challenges in fabrication of those devices to providing robust and reliable on-chip communication. Microrings resonators, the basic components of nanophotonic interconnect, may not resonate at the designated wavelength under fabrication errors (a.k.a. process variations PV) or thermal fluctuation (TF), leading to communication errors and bandwidth loss. In addition, the power overhead required to correct the drift can overturn the benefits promised by this new technology. Hence, the objective of the thesis is to maximize network bandwidth through proper arrangement among microrings and wavelengths with minimum tuning power requirement. I propose the following techniques to achieve my goals. First, I will present a series of solutions, called ``MinTrim'', to address the wavelength drifting problem of microrings and subsequent bandwidth loss problem of an optical network, due to the PV. Next, to mitigate bandwidth loss and performance degradation caused by PV and TF, I will propose an architecture-level approach, ``BandArb'', which allocates the bandwidth at runtime according to network demands and temperature with low computation overhead. Finally, I will conclude the thesis and discuss the future works in this field

Physical Layer Modeling and Optimization of Silicon Photonic Interconnection Networks

The progressive blooming of silicon photonics technology (SiP) has indicated that optical interconnects may substitute the electrical wires for data movement over short distances in the future. Silicon Photonics platform has been the subject of intensive research for more than a decade now and its prospects continue to emerge as it enjoys the maturity of CMOS manufacturing industry. SiP foundries all over the world and particularly in the US (AIM Photonics) have been developing reliable photonic design kits (PDKs) that include fundamental SiP building blocks such as wavelength selective modulators and tunable filters. Microring resonators (MRR) are hailed as the most compact devices that can perform both modulation and demodulation in a wavelength division multiplexed (WDM) transceiver design. Although the use of WDM can reduce the number of fibers carrying data, it also makes the design of transceivers challenging. It is probably acceptable to achieve compactness at the expense of somewhat higher transceiver cost and power consumption. Nevertheless, these two metrics should remain close to their roadmap values for Datacom applications. An increase of an order of magnitude is clearly not acceptable. For example costs relative to bandwidth for an optical link in a data center interconnect will have to decrease from the current $5/Gbps down to <$1/Gbps. Additionally, the transceiver itself must remain compact. The optical properties of SiP devices are subject to various design considerations, operation conditions, and optimization procedures. In this thesis, the general goal is to develop mathematical models that can accurately describe the thermo-optical and electro-optical behavior of individual SiP devices and then use these models to perform optimization on the parameters of such devices to maximize the capabilities of photonic links or photonic switch fabrics for datacom applications. In Chapter 1, Introduction, we first provide an overview of the current state of the optical transceivers for data centers and datacom applications. Four main categories for optical interfaces (Pluggable transceivers, On-board optics, Co-packaged optics, monolithic integration) are briefly discussed. The structure of a silicon photonic link is also briefly introduced. Then the direction is shifted towards optical switching technologies where various technologies such as free space MEMS, liquid crystal on silicon (LCOS), SOA-based switches, and silicon-based switches are explored. In Chapter 2, Silicon Photonic Waveguides, we present an extensive study of the silicon-on-insulator (SOI) waveguides that are the basic building blocks of all of the SiP devices. The dispersion of Si and SiO2 is modeled with Sellmiere equation for the wavelength range 1500–1600 nm and then is used to calculate the TE and TM modes of a 2D slab waveguide. There are two reasons that 2D waveguides are studied: first, the modes of these waveguides have closed form solutions and the modes of 3D waveguides can be approximated from 2D waveguides based on the effective index method. Second, when the coupling of waveguides is studied and the concept of curvature function of coupling is developed, the coupled modes of 2D waveguides are used to show that this approach has some inherent small error due to the discretization of the nonuniform coupling. This chapter finishes by describing the coefficients of the sensitivity of optical modes of the waveguides to the geometrical and material parameters. Perturbation theory is briefly presented as a way to analytically examine the impact of small perturbations on the effective index of the modes. In Chapter 3, Compact Modeling Approach, the concept of scattering matrix of a multi-port silicon photonic device is presented. The elements of the S-matrix are complex numbers that relate the amplitude and phase relationships of the optical models in the input and output ports. Based on the scattering matrix modeling of silicon photonics devices, two methods of solving photonic circuits are developed: the first one is based on the iteration for linear circuits. The second approach is based on the construction of an equivalent signal flow graph (SFG) for the circuit. We show that the SFG approach is very efficient for circuits involving microring resonator structures. Not only SFG can provide the solution for the transmission, it also provides the signal paths and the closed-form solution based on the Mason’s graph formula. We also show how the SFG method can be utilized to formulate the backscattering effects inside a ring resonator. In Chapter 4, Scalability of Silicon Photonic Switch Fabrics, we develop the models for electro-optic Mach-Zehnder switch elements (2×2). For the electro-optic properties, the empirical Soref’s equations are used to characterize how the loss and index of silicon changes when the charge carrier density is changed. We then use our photonic circuit solver based on the iteration method to find accurate result of light propagation in large-scale switch topologies (e.g. 4×4, and 8×8). The concept of advanced path mapping based on physical layer evaluation of the switch fabric is introduced and used to develop the optimum routing tables for 4×4 and 8×8 Benes switch topologies. In Chapter 5, Design space of Microring Resonators, we introduce the concept of curvature function of coupling to mathematically characterize the coupling coefficient of a ring resonator to a waveguide as a function of the geometrical parameters (ring radius, coupling gap, width and height of waveguides) and the wavelength. Extensive 2D and 3D FDTD simulations are carried out to validate our modeling approach. Experimental demonstrations are also used to not only further validate our modeling of coupling, but also to extract an empirical power-law model for the bending loss of the ring resonators as a function the radius. By combining these models, we for the first time present a full characterization of the design space of microring resonators. Moreover, the value of this discussion will be further apparent when the scalability of a silicon photonic link is studied. We will show that the FSR of the rings determines the optical bandwidth but it also impacts the properties of the ring resonators. In Chapter 6, Thermo-optic Efficiency of Microheaters, we develop analytical models for the thermo-optic properties of SiP waveguides. For the thermo-optic properties, the concept of thermal impulse response is mathematically developed for integrated micro-heaters. The thermal impulse response is a key function that determines the tradeoff between heating efficiency and heating speed (thermal bandwidth), as well as allows us to predict the pulse-width-modulation (PWM) optical response of the heater-waveguide system. One of the motivations behind this study was to find the highest possible efficiency for thermal tuning of microring resonators to use it in the evaluation of the energy consumption of a photonic link. The results indicate 2 nm/mW which is in agreement with the trends that we see in the literature. In Chapter 7, Crosstalk Penalty, we theoretically and experimentally investigate the optical crosstalk effects in microring-based silicon photonic interconnects. Both inter-channel crosstalk and intra-channel crosstalk are investigated and approximate equations are developed for their corresponding power penalties. Inclusion of the inter-channel crosstalk is an important part of our final analysis of a silicon photonic link. In Chapter 8, Scalability of Silicon Photonic Links, we present the analysis of a WDM silicon photonics point-to-point link based on microring modulators and microring wavelength filters. Our approach is based on the power penalty analysis of non-return-to-zero (NRZ) signals and Gaussian noise statistics. All the necessary equations for the optical power penalty calculations are presented for microring modulators and filters. The first part of the analysis is based on various ideal assumptions which lead to a maximum capacity of 2.1 Tb/s for the link. The second part of the analysis is carried out with more realistic assumptions on the photonic elements in the link, culminating in a maximum throughput of 800 Gb/s. We also provide estimations of the energy/bit metric of such links based on the optimized models of electronic circuits in 65 nm CMOS technology

Design exploration and measurement benchmark of integrated-circuits based on graphene field-effect-transistors : towards wireless nanotransceivers

This doctoral thesis approaches the design requirements for future high / ultra-high data rate (from 100 Mbps to 100 Gbps) nanotransceivers (nanoTRx) applied to wireless nanonetworks which imply short/ultra-short distance ranges (3 cm ¿ 3 m). It explores graphene field-effect-transistors (GFET), by simulation against measurement benchmarks, as a potential solution for implementing large-signal high-frequency circuits, by virtue of graphene¿s one-atom thickness and high carrier-mobility extraordinary properties. Finally, the thesis discusses the challenges faced by GFETs, such as zero-bandgap and high metal-graphene contact-resistance, to be able to propose improvements for achieving the initial proposed goals. Chemical-Vapour-Deposition (CVD) GFET fabrication is considered, which is very promising for large-scale manufacturing (CMOS process compatible), and for that fast-computing large-signal compact modeling for complex circuit design is analysed in depth and optimized, and consequently a set of diverse large-signal static and dynamic GFET circuits are simulated and benchmarked against available measurements assessing the accuracy of the proposed models and deriving scaling prospects. An optimization of the current-to-voltage (I-V) characteristic of a GFET compact model, based upon drift-diffusion carrier transport, is presented. The improved accuracy at the Dirac point extends the model usability for GFETs when scaling parameters such as voltage supply (Vdd), gate length (L), dielectric thickness (tox) and carrier mobility (¿) for large-signal design exploration in circuits. The model accuracy is demonstrated through parameters fitting to measurements taken from CVD GFETs fabricated in the University of Siegen and Technical University of Milan. The script has been written in a standard behavioural language (Verilog-A), and extensively run in a commercial analog circuit simulator (Cadence environment) demonstrating its robustness. Besides a simple capacitance-to-voltage model (C-V), a small-signal parasitic capacitance model fitted to dynamic measurements for self-aligned CVD GFETs available in the literature is added, enabling to forecast maximum-frequency-of-oscillation (fmax) trends for future scaling. A design-oriented characterization of complementary inverter circuits (INV) based on GFETs is presented as well. Our proposed compact model is benchmarked at the circuit level against another compact model based on a virtual-source approach. Furthermore, a benchmark between simulations and measurements of already fabricated CVD GFET INVs is performed, and performance trends when scaling are derived. The same process is repeated for a more complex circuit, namely GFET ring-oscillators (RO). The transient regime simulations yield performance metrics in terms of oscillation frequency (fosc) and dynamic voltage range (¿Vosc), and consequently, against these metrics, a comprehensive design space exploration covering as input design variables parameters as tox, L, and Vdd is carried out. Being aware of the lack of voltage amplification shown by existing GFETs, the design exploration of a cascode amplifier (CAS) targeted to increase voltage gain (Av) by decreasing its output conductance (go) is presented. GFET CAS are simulated to provide design guidelines, they are accordingly fabricated and consequently measured. Performance metrics are provided in terms of go, transconductance (gm) and hence Av. Against these metrics, a quantitative comparison between CAS and GFETs is performed and conclusions are derived. Finally, conclusions on GFETs suitability for future nanoTRX are elaborated. The derived publications come from international collaborations with the Royal Institute of Technology (KTH) in Sweden from 2012 to 2014, and the University of Siegen in Germany from 2014 to 2016.Esta tesis doctoral trata de identificar los requisitos de diseño para nano-ransceptores (nanoTRx) con datos de alta velocidad (de 100 Mbps a 100 Gbps) aplicados a nano-redes inal ámbricas que implican rangos de alcance cortos u ultra-cortos (3 cm - 3 m ); explora FETs de grafeno (GFET), mediante simulaciones y mediciones, como una solución potencial para la implementación de circuitos de alta frecuencia de gran señal, gracias a las extraordinarias propiedades del grafeno como su espesor de un solo átomo y sus portadores de alta movilidad; y finalmente, se discuten los desafíos a los que se enfrentan los GFETs, como la falta de banda prohibida y la alta resistencia de contacto, para lograr proponer alternativas y poder alcanzar los objetivos iniciales propuestos. Las publicaciones derivadas provienen de Colaboraciones internacionales con el KTH en Suecia de 2012 a 2014, y la UniSiegen en Alemania de 2014 a 2016. Se introducen la técnica CVD como un proceso de fabricación de GFETs a gran escala, compatible con tecnología CMOS, muy prometedor; y el modelado compacto de gran señal y computación veloz para el diseño de circuitos complejos es optimizados y analizado en profundidad, Consecuentemente circuitos de gran señal (estáticos y dinámicos) basados en GFET son simulados y comparados con las mediciones disponibles para evaluar la precisi ón de los modelos propuestos y derivar prospecciones de escalado. Se propone una optimización de la característica corriente-voltaje (I-V) de un modelo compacto GFET, basado en el transporte de portadores difusi ón-deriva. La precisión mejorada en el punto de Dirac extiende la usabilidad del modelo para GFETs cuando se dimensionan parámetros para la exploración en diseños de circuitos de gran señal, tales como el voltaje de alimentación (Vdd), la longitud de puerta (L), el espesor diel éctrico (tOX) y la movilidad de portadores (U). La precisión del modelo se demuestra a través de parámetros que se ajustan a mediciones tomadas a partir de CVD GFETs fabricados en la UniSiegen y en el PoliMi. El programa se ha escrito en Verilog-A y se ejecuta extensivamente en un simulador de circuitos anal ógico comercial donde se demuestra su robustez. Además, se lleva a cabo la parametrización de un modelo capacidad-voltaje (C-V) que se ajusta a las mediciones de alta frecuencia de CVD GFETs disponibles en la literatura científica, lo que permite la predicción de la fMAX para el escalado de futuros GFETs. También se presenta una caracterización orientada al diseño de circuitos inversores complementarios (INV) basados en GFETs. Nuestro modelo compacto propuesto se compara a nivel de circuito con otro modelo compacto basado en fuentevirtual. A continuación, se lleva a cabo una comparación a nivel circuito entre las simulaciones y las medidas de INVs ya fabricados basados en CVD GFET, y se obtienen las tendencias de comportamiento al escalarlos. Se repite el mismo proceso para un circuito más complejo, los llamados osciladores-en-anillo GFET (RO). Las simulaciones basadas en transitorios producen métricas de rendimiento en términos de frecuencia de oscilación (fosc) y rango dinámico de voltaje (Vosc), por lo tanto, contra estas métricas, se lleva a cabo una exploración exhaustiva de diseño que abarca Parámetros de variables de diseño como tOX, L y Vdd. Al ser conscientes de la falta de amplificación de voltaje mostrada por los GFETs existentes, se presenta la exploración de diseño de un amplificador cascodo (CAS) diseñado para incrementar la amplificación de voltaje (Av) disminuyendo su conductancia de salida (go). Los GFET CAS son simulados para proporcionar guías de diseño, luego fabricadas y finalmente medidas. Se proporcionan métricas de rendimiento en términos de go, gm, y consecuentemente Av. Frente a estas métricas, se realiza una comparación cuantitativa entre CAS y GFETs y se derivan las conclusiones. Finalmente, se elaboran las conclusiones sobre la idoneidad de los GFET para futuros nanoTR

Ultra-High Capacity Silicon Photonic Interconnects through Spatial Multiplexing

The market for higher data rate communication is driving the semiconductor industry to develop new techniques of writing at smaller scales, while continuing to scale bandwidth at low power consumption. The question arises of how to continue to sustain this trend. Silicon photonic (SiPh) devices offer a potential solution to the electronic interconnect bandwidth bottleneck. SiPh leverages the technology commensurate of decades of fabrication development with the unique functionality of next-generation optical interconnects. Finer fabrication techniques have allowed for manufacturing physical characteristics of waveguide structures that can support multiple modes in a single waveguide. By refining modal characteristics in photonic waveguide structures, through mode multiplexing with the asymmetric y-junction and microring resonator, higher aggregate data bandwidth is demonstrated via various combinations of spatial multiplexing, broadening applications supported by the integrated platform. The main contributions of this dissertation are summarized as follows. Experimental demonstrations of new forms of spatial multiplexing combined together exhibit feasibility of data transmission through mode-division multiplexing (MDM), mode-division and wavelength-division multiplexing (MDM-WDM), and mode-division and polarization-division multiplexing (MDM-PDM) through a C-band, Si photonic platform. Error-free operation through mode multiplexers and demultiplexers show how data can be viably scaled on multiple modes and with existing spatial domains simultaneously. This work opens up new avenues for scaling bandwidth capacity through leveraging orthogonal domains available on-chip, beyond what had previously been employed like WDM and time-division multiplexing (TDM). Furthermore, we explore expanding device channel support from two to three arms. Finding that a slight mismatch in the third arm can increase crosstalk contributions considerably, especially when increasing data rate, we explore a methodical way to design the asymmetric y-junction device by considering its angles and multiplexer/demultiplexer arm width. By taking into consideration device fabrication variations, we turn towards optimizing device performance post-fabrication. Through ModePROP simulations, optimizing device performance dynamically post-fabrication is analyzed, through either electro-optical or thermo-optical means. By biasing the arm introducing the slight spectral offset, we can quantifiably improve device performance. Scaling bandwidth is experimentally demonstrated through the device at 3 modes, 2 wavelengths, and 40 Gb/s data rate for 240 Gb/s aggregate bandwidth, with the potential to reduce power penalty per the device optimization process we described. A main motivation for this on-chip spatial multiplexing is the need to reduce costs. As the laser source serves as the greatest power consumer in an optical system, mode-division multiplexing and other forms of spatial multiplexing can be implemented to push its potentially prohibitive cost metrics down. While the device introduces loss, through imperfect mode isolation, as device fabrication improves, tolerance can increase as well. Meanwhile, the rate that laser power consumption increases as supported wavelengths scales is shown to be much faster than the loss introduced by scaling on-chip bandwidth multi-modally. Future generations of ultra-high capacity devices through spatial multiplexing is explored. Already various systems can be implemented multimodally, with the design features serving as useful for other components. Central to photonic network-on-chips, a multimodal switch fabric, composed of microring resonators, is demonstrated to have error-free operation of 1x2 switching of 10 Gb/s data. These contributions aim to scale bandwidth to ultra-high capacity, while ameliorating any imperfect design, through multiple routes conjoined with on-chip spatial multiplexing, and they constitute the bulk of this dissertation. For the latter part, we turn to the issue of integrating a photonic device for dynamic power reallocation in a system. Specifically, we utilize a 4x4 nonblocking switch fabric composed of Mach-Zehnder interferometers that switch both electro-optically and thermo-optically at ns and μs rates respectively. In order to demonstrate an intelligent platform capable of dynamically multicasting data and reallocating power as needed by the system, we must first initialize the switch fabric to control with an electronic interface. A dithering mechanism, whereby exact cross, bar, and sub-percentage states are enforced through the device, is described here. Such a method could be employed for actuating the device table of bias values to states automatically. We then employ a dynamic power reallocation algorithm through a data acquisition unit, showing real-time channel recovery for channels experiencing power loss by diverting power from paths that could tolerate it. The data that is being multicast through the system is experimentally shown to be error-free at 40 Gb/s data rate, when transmitting from one to three clients and going from automatic bar/cross states to equalized power distribution. For the last portion of this topic, the switch fabric was inserted into a high-performance computing system. In order to run benchmarks at 10 Gb/s data ontop of the switch fabric, a newer model of the control plane was implemented to toggle states according to the command issued by the server. Such a programmable mechanism will prove necessary in future implementations of optical subsystems embedded inside larger systems, like data centers. Beyond the specific control plane demonstrated, the idea of an intelligent photonic layer can be applied to alleviate many kinds of optical channel abnormalities or accommodate for switching based on different patterns in data transmission. Besides spatial-multiplexing, expanding on-chip bandwidth can be accomplished by extension of the wavelength detection regime to a longer regime. Experimental demonstration of photodetection at 1.9 μm is shown with Si+-doped Si photodetectors at 1 Gb/s data operation featuring responsivities of .03 AW−1 at 5 V bias. The same way of processing these Si ribbed waveguide photodetectors can garner even longer wavelength operation at 2.2 μm wavelength. Finally, the experimental demonstration of a coherent perfect absorption Si modulator is exhibited, showing a viable extinction ratio of 24.5 dB. Using this coherent perfect absorption mechanism to demodulate signals, there is the added benefit of differential reception. Currently, an automated process for data collection is employed at a faster time scale than instabilities present in fibers in the setup with future implementations eliminating the off-chip phase modulator for greater signal stability. The field of SiPh has developed to a stage where specific application domains can take off and compete according to industrial-level standards. The work in this dissertation contributes to experimental demonstration of a newly developing area of mode-division multiplexing for substantially increasing bandwidth on-chip. While implementing the discussed photonic devices in dynamic systems, various attributes of integrated photonics are leveraged with existing electronic technologies. Future generations of computing systems should then be designed by implementing both system and device level considerations