Linear-Phase FIR Digital Filter ‎Design with Reduced Hardware Complexity using Discrete Differential Evolution

Optimal design of xed coe cient nite word length linear phase FIR digital lters for custom ICs has been the focus of research in the past decade. With the ever increasing demands for high throughput and low power circuits, the need to design lters with reduced hardware complexity has become more crucial. Multiplierless lters provide substantial saving in hardware by using a shift add network to generate the lter coe cients. In this thesis, the multiplierless lter design problem is modeled as combinatorial optimization problem and is solved using a discrete Di erential Evolution algorithm. The Di erential Evolution algorithm\u27s population representation adapted for the nite word length lter design problem is developed and the mutation operator is rede ned for discrete valued parameters. Experiments show that the method is able to design lters up to a length of 300 taps with reduced hardware and shorter design times

Linear-Phase FIR Digital Filter Design with Reduced Hardware Complexity using Extremal Optimization

Extremal Optimization is a recent method for solving hard optimization problems. It has been successfully applied on many optimization problems. Extremal optimization does not share the disadvantage of most of the other evolutionary algorithms, which is the tendency to converge into local minima. Design of finite word length FIR filters using deterministic techniques can guarantee optimality at the expense of exponential increase in computational complexity. Alternatively, Evolutionary Algorithms are capable of converging very fast to a minimum, but have higher chances of failure if the ratio of feasible solutions is very less in the search space. In this thesis, a set of feasible solutions are determined by linear programming. In the second step, Extremal Optimization is used to further refine these results. This strategy helps by reducing the search space for the EO algorithm and is able to find good solutions in much shorter time than the existing methods

Automatisoitu vuo suodinten laitteistokuvauksen tuottamiseen

Digitaalisia suotimia käytetään signaalien käsittelyyn monilla eri tekniikan alueilla, kuten telekommunikaatiossa, kuvankäsittelyssä ja lääketieteellisissä laitteissa. Ne ovat niin yleisiä, että insinöörit käyttävät paljon aikaa ja resursseja niiden toteuttamiseen ja verifioimiseen. Koska yleisimpien suotimien rakenne on melko yksinkertainen, niiden luominen voidaan automatisoida generaattorin avulla. Tässä diplomityössä Nokia Networksin vaatimukset kartoitetaan automatisoidun suodinten laitteistokuvauksen tuottamisvuon kehittämiseksi. Erilaisia tuottamismenetelmiä vertaillaan, mutta lopulta päädytään kehittämään oma generaattori. Se luo suotimia yhdistelemällä osia käsinkirjoitetusta RTL:stä. Lopputuloksena on automatisoitu vuo, joka tukee vakiokertoimilla varustettuja, yhden tai useamman kanavan FIR-suotimia. Käyttäjän tulee syöttää kertoimet ja haluttu datanleveys Matlab-skriptiin. Ajettaessa skripti luo suotimen ja verifioi sen. Vuo tukee sekä ASIC- että FPGA-teknologioita.Digital filters are used to process signals in many fields like telecommunications, image processing and in medical equipment. They are so omnipresent that engineers are building and verifying those all the time, using a lot of resources. As the structure of a basic filter is quite simple, savings could be made by automatizing the creation of filters. In this Thesis the requirements of Nokia Networks are analyzed to build an automatized filter generation flow. Different tools are evaluated, but finally a custom generator is built. It crafts filters from pieces of hand-written RTL. The end result is an automated flow which supports single and multichannel FIR filters with constant coefficients. The user has to input the coefficients to a Matlab script with the desired data widths. The filter is then generated and verified by running the script. The flow supports both ASIC and FPGA technologies

Automatisoitu vuo suodinten laitteistokuvauksen tuottamiseen

Digitaalisia suotimia käytetään signaalien käsittelyyn monilla eri tekniikan alueilla, kuten telekommunikaatiossa, kuvankäsittelyssä ja lääketieteellisissä laitteissa. Ne ovat niin yleisiä, että insinöörit käyttävät paljon aikaa ja resursseja niiden toteuttamiseen ja verifioimiseen. Koska yleisimpien suotimien rakenne on melko yksinkertainen, niiden luominen voidaan automatisoida generaattorin avulla. Tässä diplomityössä Nokia Networksin vaatimukset kartoitetaan automatisoidun suodinten laitteistokuvauksen tuottamisvuon kehittämiseksi. Erilaisia tuottamismenetelmiä vertaillaan, mutta lopulta päädytään kehittämään oma generaattori. Se luo suotimia yhdistelemällä osia käsinkirjoitetusta RTL:stä. Lopputuloksena on automatisoitu vuo, joka tukee vakiokertoimilla varustettuja, yhden tai useamman kanavan FIR-suotimia. Käyttäjän tulee syöttää kertoimet ja haluttu datanleveys Matlab-skriptiin. Ajettaessa skripti luo suotimen ja verifioi sen. Vuo tukee sekä ASIC- että FPGA-teknologioita.Digital filters are used to process signals in many fields like telecommunications, image processing and in medical equipment. They are so omnipresent that engineers are building and verifying those all the time, using a lot of resources. As the structure of a basic filter is quite simple, savings could be made by automatizing the creation of filters. In this Thesis the requirements of Nokia Networks are analyzed to build an automatized filter generation flow. Different tools are evaluated, but finally a custom generator is built. It crafts filters from pieces of hand-written RTL. The end result is an automated flow which supports single and multichannel FIR filters with constant coefficients. The user has to input the coefficients to a Matlab script with the desired data widths. The filter is then generated and verified by running the script. The flow supports both ASIC and FPGA technologies

Multiple Real-Constant Multiplication for Computationally Efficient Implementation of Digital Transforms

The need to multiply signals by vectors (or matrices) of constants is fundamental and frequently arises in many areas of electrical and computer engineering.In their hardware implementations, performance issues such as circuit area, delay, and power consumption heavily influence the design process.It is well known that multiplication of a signal by a constant can be implemented multiplierless as a network of shifts and additions, and that these computational networks, termed shift-add networks, can lend to higher performing circuit implementations than when using general multipliers.There is a rich body of work on the optimization of shift-add networks, known as the multiple constant multiplication (MCM) problem.However, the optimization strategies that have been developed for the MCM traditionally assume that the vector multiplications being optimized always stem from integer constants.This assumption breaks down for many real-world applications, where the target constants for MCM optimization are real numbers rather than integers.In these situations there is flexibility in how constants are quantized in digital circuits that can be leveraged.Thus, it is desirable to have a method of jointly optimizing both the constant quantization error and the shift-add network simultaneously.This dissertation addresses this need by providing a problem framework and algorithms for joint quantization/MCM optimization and, through a series of experiments, shows that there is a potential for tremendous benefit when the optimization of quantization and shift-add networks is executed in one unified problem framework.After reviewing the relevant work, this dissertation rigorously develops the aforementioned joint optimization framework, describing the metrics used for quantization error, and culminates in a formal problem statement.We call this joint optimization problem the multiple real-constant multiplication problem (MRCM) in order to distinguish it from the traditional MCM problem that operates exclusively with integer constants, which we hereafter refer to as the multiple integer-constant multiplication (MICM) problem.Then, we consider three different cost models used for evaluating shift-add networks and, with each model, we determine the potential advantages of using our MRCM framework over the traditional MICM approach.First, we consider the traditional adder-count cost model.We start by formally defining the MRCM problem in the context of this cost model, and then describe a series of theoretical developments centered around finitizing and pruning the search space, leading to an efficient algorithm for solving the problem.Next, via extensive randomized experiments, we show that our joint framework leads to a reduction on the number of adders by 15%–60% on moderate size problems.In particular, for vectors of arbitrary constants, we show a possibility for 20%–60% reduction with less than 10% vector approximation error for both frameworks, whereas for vectors of low-pass filter coefficients, a 15%–30% reduction is possible without exceeding 10% error in frequency response.Second, we consider an adder-bits cost model, whereby instead of simply counting the number of adders, we compute the combined bitwidth of all the adders.To solve the MRCM problem in this context, we introduce two search algorithms—one greedy and one optimal, each guided by a novel MRCM-aware heuristic.Next, we discuss a randomized experiment, in which we compare both algorithms to an MICM-targeted heuristic.We observe that the greedy search finds solutions with an average cost improvement of 13% over the MICM solution with the trials considered, and the optimal search finds an additional improvement of 6%.Third, we consider a prominent gate-level cost model from the literature that.This gate-level model consider the bitwidths of an adder's inputs and output along with the relative alignment of the inputs/output due to bit shifting, when computing the adder cost.To solve the MRCM problem in this context, a novel greedy algorithm is developed that uses a functional programming approach to solving the MRCM problem.Next, we experimentally show this algorithm to offer an improvement of up to 18%, over a competing MICM algorithm, on small instances having 20 8-bit constants, increasing to up to 59% improvement on larger instances having 80 5-bit constants.Finally, we conclude the work by offering recommendations for possible future work in the development of efficient MRCM algorithms and novel problem formulations for optimizing MCM circuits

Energy efficient hardware acceleration of multimedia processing tools

The world of mobile devices is experiencing an ongoing trend of feature enhancement and generalpurpose multimedia platform convergence. This trend poses many grand challenges, the most pressing being their limited battery life as a consequence of delivering computationally demanding features. The envisaged mobile application features can be considered to be accelerated by a set of underpinning hardware blocks Based on the survey that this thesis presents on modem video compression standards and their associated enabling technologies, it is concluded that tight energy and throughput constraints can still be effectively tackled at algorithmic level in order to design re-usable optimised hardware acceleration cores. To prove these conclusions, the work m this thesis is focused on two of the basic enabling technologies that support mobile video applications, namely the Shape Adaptive Discrete Cosine Transform (SA-DCT) and its inverse, the SA-IDCT. The hardware architectures presented in this work have been designed with energy efficiency in mind. This goal is achieved by employing high level techniques such as redundant computation elimination, parallelism and low switching computation structures. Both architectures compare favourably against the relevant pnor art in the literature. The SA-DCT/IDCT technologies are instances of a more general computation - namely, both are Constant Matrix Multiplication (CMM) operations. Thus, this thesis also proposes an algorithm for the efficient hardware design of any general CMM-based enabling technology. The proposed algorithm leverages the effective solution search capability of genetic programming. A bonus feature of the proposed modelling approach is that it is further amenable to hardware acceleration. Another bonus feature is an early exit mechanism that achieves large search space reductions .Results show an improvement on state of the art algorithms with future potential for even greater savings

OPTIMIZATION OF FPGA-BASED PROCESSOR ARCHITECTURE FOR SOBEL EDGE DETECTION OPERATOR

This dissertation introduces an optimized processor architecture for Sobel edge detection operator on field programmable gate arrays (FPGAs). The processor is optimized by the use of several optimization techniques that aim to increase the processor throughput and reduce the processor logic utilization and memory usage. FPGAs offer high levels of parallelism which is exploited by the processor to implement the parallel process of edge detection in order to increase the processor throughput and reduce the logic utilization. To achieve this, the proposed processor consists of several Sobel instances that are able to produce multiple output pixels in parallel. This parallelism enables data reuse within the processor block. Moreover, the processor gains performance with a factor equal to the number of instances contained in the processor block. The processor that consists of one row of Sobel instances exploits data reuse within one image line in the calculations of the horizontal gradient. Data reuse within one and multiple image lines is enabled by using a processor with multiple rows of Sobel instances which allow the reuse of both the horizontal and vertical gradients. By the application of the optimization techniques, the proposed Sobel processor is able to meet real-time performance constraints due to its high throughput even with a considerably low clock frequency. In addition, logic utilization of the processor is low compared to other Sobel processors when implemented on ALTERA Cyclone II DE2-70

Digital Filters and Signal Processing

Digital filters, together with signal processing, are being employed in the new technologies and information systems, and are implemented in different areas and applications. Digital filters and signal processing are used with no costs and they can be adapted to different cases with great flexibility and reliability. This book presents advanced developments in digital filters and signal process methods covering different cases studies. They present the main essence of the subject, with the principal approaches to the most recent mathematical models that are being employed worldwide