Oscillator phase noise: a tutorial

Linear time-invariant (LTI) phase noise theories provide important qualitative design insights but are limited in their quantitative predictive power. Part of the difficulty is that device noise undergoes multiple frequency translations to become oscillator phase noise. A quantitative understanding of this process requires abandoning the principle of time invariance assumed in most older theories of phase noise. Fortunately, the noise-to-phase transfer function of oscillators is still linear, despite the existence of the nonlinearities necessary for amplitude stabilization. In addition to providing a quantitative reconciliation between theory and measurement, the time-varying phase noise model presented in this tutorial identifies the importance of symmetry in suppressing the upconversion of 1/f noise into close-in phase noise, and provides an explicit appreciation of cyclostationary effects and AM-PM conversion. These insights allow a reinterpretation of why the Colpitts oscillator exhibits good performance, and suggest new oscillator topologies. Tuned LC and ring oscillator circuit examples are presented to reinforce the theoretical considerations developed. Simulation issues and the accommodation of amplitude noise are considered in appendixes

FULLY INTEGRATED HIGH-FREQUENCY CLOCK GENERATION AND SYNCHRONIZATION TECHINIQUES

Department of Electrical EngineeringThis thesis presents clock generation and synchronization techniques for RF wireless communication. First, it deals with voltage-controlled oscillators (VCOs) for local oscillators (LO) in transceivers, and secondly delay-locked loops for synchronization. For the high-performance LO, VCO is one of the key blocks. LC VCOs and ring VCOs are commonly-used types. Their characteristics are varied for different frequency bands. In this thesis, two types of VCOs, LC VCO and ring VCO, are presented with specific applications. For the multi-clock generator which could be used for carrier aggregation or frequency hopping, ring-type digitally controlled oscillator (DCO) was designed covering 900-1200 MHz with -165 dB FOM. For the multi-band frequency synthesizer which could be used for 5G communication with backward compatibility, three LC VCOs are designed which frequency range of 25-30 GHz for 5G, 5.2-6.0 GHz for LTE, 2.7-4.2 GHz for 2G-3G communication, respectively. For the clock synchronization in RF communications, a delay-locked loop (DLL) using a digital-to-analog converter (DAC) based band-selecting circuit (BSC) was presented to achieve a wide harmonic-locking-free frequency range. The BSC used the proposed exponential digital-to-analog converter (EDAC) to generate a collection of initial control voltages which follow a sequence of geometric with satisfying the condition for preventing harmonic locking problem. Therefore, the BSC can cover a much wider frequency range which is free from harmonic locking problem compared to initial band selection techniques using conventional, linear DAC (LDAC) that have a set of control voltages of arithmetic sequence. In this thesis, the DLL was implemented in a 65-nm CMOS process, and it had a measured frequency range from 100 to 1500 MHz which range is free from harmonic locking. The measure rms jitter and 1-MHz phase noise at 1000 MHz were 1.99 ps and ?28 dBc/Hz, respectively. The DLL consumes 5.5 mW and its active area was 0.052 mm2.clos

Design And Implementation Of Up-Conversion Mixer And Lc-Quadrature Oscillator For IEEE 802.11a WLAN Transmitter Application Utilizing 0.18 Pm CMOS Technology [TK7871.99.M44 H279 2008 f rb].

Perlumbaan implementasi litar terkamil radio, dengan kos yang rendah telah menggalakkan penggunaan teknologi CMOS. The drive for cost reduction has led to the use of CMOS technology for highly integrated radios

A novel tuning technique for distributed voltage controlled oscillators

A novel current-steering delay-balanced tuning technique for distributed voltage controlled oscillators (DVCO) is demonstrated. This tuning technique is used to design a DVCO operating at 10 GHz in a 0.35 μm CMOS technology. The DVCO is continuously tunable between 9.9 and 10.3 GHz. Special attention is paid to the layout issues for the high frequency design

A design approach for integrated CMOS LC-tank oscillators using bifurcation analysis

Electrical oscillators play a decisive role in integrated transceivers for wired and wireless communication systems. In this context the study of fully integrated differential VCOs has received attention. In this paper formulas for investigations of the stability as well as the amplitude of CMOS LC tank oscillators are derived, where an overall model of nonlinear gain elements is used. By means of these results we are able to present an improved design approach which gives a deeper insight into the functionality of LC tank VCOs

Efficient and Interference-Resilient Wireless Connectivity for IoT Applications

With the coming of age of the Internet of Things (IoT), demand on ultra-low power (ULP) and low-cost radios will continue to boost tremendously. The Bluetooth-Low-energy (BLE) standard provides a low power solution to connect IoT nodes with mobile devices, however, the power of maintaining a connection with a reasonable latency remains the limiting factor in defining the lifetime of event-driven BLE devices. BLE radio power consumption is in the milliwatt range and can be duty cycled for average powers around 30μW, but at the expense of long latency. Furthermore, wireless transceivers traditionally perform local oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Innovations in both the system architecture and circuits implementation are essential for the design of truly ubiquitous receivers for IoT applications. This research presents two porotypes as back-channel BLE receivers, which have lower power consumption while still being robust in the presents of interference and able to receive back-channel message from BLE compliant transmitters. In addition, the first crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard using a GFSK-Modulated BLE Packet is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162942/1/abdulalg_1.pd

Ultra-Low Power Wake Up Receiver For Medical Implant Communications Service Transceiver

This thesis explores the specific requirements and challenges for the design of a dedicated wake-up receiver for medical implant communication services equipped with a novel “uncertain-IF†architecture combined with a high – Q filtering MEMS resonator and a free running CMOS ring oscillator as the RF LO. The receiver prototype, implements an IBM 0.18μm mixed-signal 7ML RF CMOS technology and achieves a sensitivity of -62 dBm at 404MHz while consuming \u3c100 μW from a 1 V supply

12???14.5 GHZ DIGITALLY CONTROLLED OSCILLATOR USING A HIGH-RESOLUTION DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER

Department of Electrical EngineeringThis thesis focuses on the design of digitally-controlled oscillators (DCO) for ultra-low-jitter digital phase-locked-loops (PLL), which requires very fine frequency resolution and low phase noise performance. Before going details of the design, fundamentals of the digital-to-analog converter (DAC), delta-sigma modulator (DSM), LC voltage-controlled oscillator (VCO) are discussed in Chapters 2, 3, and 4 respectively. Detailly, Chapter 2 begins with the basic operations of the digital-toanalog converters. Plus, several types of DACs and their properties are discussed. For instance, resistorbased DAC or current source-based DAC. In Chapter 3, the backgrounds of DSMs are presented. The reason why DSMs are indispensable components in fractional number generation is presented. The meaning of the randomization and noise shaping in DSMs is discussed then high-order noise shaping DSMs are explained as well. Chapter 4, starts with the LC tanks. Integrated passive components are introduced such as spiral inductors, metal-insulator-metal (MIM) capacitors, and metal-oxide-metal (MOM) capacitors. The start-up of the oscillators also explained by using two approaches, the Barkhausen criterion and the negative resistance theory. Then the pros and cons of the CMOS and NMOS type topologies are stated. Finally, the phase noise in oscillators is analyzed by using the Leeson???s equation and the impulse-sensitivity function theory. In chapter 5, the detailed designs of the prototype DCO are presented. The designed DCO consists of 2nd order DSM, string resistor-based DAC, and CMOS-type LC VCO. The frequency resolutions of the proportional and integral path are different but the structures are identical. For the high-performance oscillator, iterative design is required. In the measurements, the designed DCO achieved 17 and 18 bit of frequency resolution in the proportional and integral path respectively, 12-14.5GHz of the frequency tuning range, 50 and 500MHz/V of KVCO for the main and auxiliary loop respectively, and -184.5 dB of figure of merit (FOM). The power consumption is 5.5mW and the prototype was fabricated in TSMC 65nm CMOS process.clos

Digital PLL for ISM applications

In modern transceivers, a low power PLL is a key block. It is known that with the evolution of technology, lower power and high performance circuitry is a challenging demand. In this thesis, a low power PLL is developed in order not to exceed 2mW of total power consumption. It is composed by small area blocks which is one of the main demands. The blocks that compose the PLL are widely abridged and the final solution is shown, showing why it is employed. The VCO block is a Current-Starved Ring Oscillator with a frequency range from 400MHz to 1.5GHz, with a 300μW to approximately 660μW power consumption. The divider is composed by six TSPC D Flip-Flop in series, forming a divide-by-64 divider. The Phase-Detector is a Dual D Flip-Flop detector with a charge pump. The PLL has less than a 2us lock time and presents a output oscillation of 1GHz, as expected. It also has a total power consumption of 1.3mW, therefore fulfilling all the specifications. The main contributions of this thesis are that this PLL can be applied in ISM applications due to its covering frequency range and low cost 130nm CMOS technology

Design and analysis of fully integrated differential VCOs

Oscillators play a decisive role for electronic equipment in many fields-like communication, navigation or data processing. Especially oscillators are key building blocks in integrated transceivers for wired and wireless communication systems. In this context the study of fully integrated differential VCOs has received attention. In this paper we present an analytic analysis of the steady state oscillation of integrated differential VCOs which is based on a nonlinear model of the oscillator. The outcomes of this are design formulas for the amplitude as well as the stability of the oscillator which take the nonlinearity of the circuit into account. © 2005 Copernicus GmbH