Department of Electrical EngineeringThis thesis focuses on the design of digitally-controlled oscillators (DCO) for ultra-low-jitter digital phase-locked-loops (PLL), which requires very fine frequency resolution and low phase noise performance. Before going details of the design, fundamentals of the digital-to-analog converter (DAC), delta-sigma modulator (DSM), LC voltage-controlled oscillator (VCO) are discussed in Chapters 2, 3, and 4 respectively. Detailly, Chapter 2 begins with the basic operations of the digital-toanalog converters. Plus, several types of DACs and their properties are discussed. For instance, resistorbased DAC or current source-based DAC. In Chapter 3, the backgrounds of DSMs are presented. The reason why DSMs are indispensable components in fractional number generation is presented. The meaning of the randomization and noise shaping in DSMs is discussed then high-order noise shaping DSMs are explained as well. Chapter 4, starts with the LC tanks. Integrated passive components are introduced such as spiral inductors, metal-insulator-metal (MIM) capacitors, and metal-oxide-metal (MOM) capacitors. The start-up of the oscillators also explained by using two approaches, the Barkhausen criterion and the negative resistance theory. Then the pros and cons of the CMOS and NMOS type topologies are stated. Finally, the phase noise in oscillators is analyzed by using the Leeson???s equation and the impulse-sensitivity function theory. In chapter 5, the detailed designs of the prototype DCO are presented. The designed DCO consists of 2nd order DSM, string resistor-based DAC, and CMOS-type LC VCO. The frequency resolutions of the proportional and integral path are different but the structures are identical. For the high-performance oscillator, iterative design is required. In the measurements, the designed DCO achieved 17 and 18 bit of frequency resolution in the proportional and integral path respectively, 12-14.5GHz of the frequency tuning range, 50 and 500MHz/V of KVCO for the main and auxiliary loop respectively, and -184.5 dB of figure of merit (FOM). The power consumption is 5.5mW and the prototype was fabricated in TSMC 65nm CMOS process.clos
