A novel current-steering delay-balanced tuning technique for distributed voltage controlled oscillators (DVCO) is demonstrated. This tuning technique is used to design a DVCO operating at 10 GHz in a 0.35 μm CMOS technology. The DVCO is continuously tunable between 9.9 and 10.3 GHz. Special attention is paid to the layout issues for the high frequency design

Hajimiri, Ali

Wu, Hui

English

Caltech Authors - Main

' ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland 
A NOVEL TUNING TECHNIQUE FOR DISTRIBUTED 
VOLTAGE CONTROLLED OSCILLATORS 
Hui Wu and Ali Hajimiri 
Department of Electrical Engineering 
California Institute of Technology 
Pasadena, CA 91 125, USA 
ABSTRACT 
A novel current-steering delay-balanced tuning technique for 
distributed voltage controlled oscillators (DVCO) is 
demonstrated. This tuning technique is used to design a DVCO 
operating at 10 GHz in a 0.35 p CMOS technology. The 
DVCO is continuously tunable between 9.9 and 10.3 GHz. 
Special attention is paid to the layout issues for the high 
frequency design. 
1. INTRODUCTION 
Voltage controlled oscillators (VCO) are essential building 
blocks in communication systems. Advances in wireless 
communications and broadband networks create demands for 
VCOs at microwave frequencies. On the high-speed digital 
communication front, multi-gigahertz clock-and-data recovery 
loops require low-jitter high-frequency VCOs to achieve a low 
bit-error rate. Even next generation microprocessors need multi- 
gigahertz on-chip frequency synthesizers. 
Traditionally, integrated VCOs at microwave frequencies were 
implemented using compound semiconductor (GaAs or InP) or 
silicon bipolar technology. However, CMOS is emerging as a 
promising low-cost alternative capable of integrating the 
microwave front-end with the digital-signal-processing back- 
end. It therefore provides a possible system-on-a-chip solution at 
microwave frequencies. 
It is difficult to design an LC-tank VCO on silicon substrate 
using CMOS process at frequencies close to the cut-off 
frequency (f~) of the transistors due to the small gain of devices. 
The low Q of integrated inductors and varactors exacerbate the 
situation for operation at frequencies above C-band., Therefore, 
the idea of a distributed oscillator is gaining momentum in 
CMOS RFICs. 
Distributed oscillators originate from distributed amplifiers, 
which have been studied for over 50 years [I-41. In 1992, Skvor 
er al. proposed to make a VCO by operating a distributed 
amplifier in the reverse gain mode, using the output from the 
idle drain load as the feedback output [ 5 ] .  A 4 GHz distributed 
oscillator was demonstrated using four discrete pHEMTs and 
microstrip lines on a printed circuit board [6]. In 1999, 
Kleveland et al. showed an integrated (with off-chip termination 
and bias) distributed oscillator at 17 GHz without any tuning 
capability in a 0.18 p technology [7]. The forward gain mode 
instead of reverse gain mode was used. Their results 
demonstrated that CMOS is usable for oscillator applications at 
microwave frequencies. 
Despite these advances, tuning remains a problem in integrated 
distributed oscillators. Since distributed oscillators usually 
operate at frequencies close to the devicefr, there is not enough 
gain to lose in tuning. Consequently, the low Q integrated 
varactors can hardly be used due to their high loss. Nor can the 
tuning scheme in [6] be applied since it cannot provide enough 
gain in CMOS technology. Therefore, a new tuning scheme 
must be developed. 
In this paper, we first discuss the basic principle and design 
issues of DVCOs. Then a novel tuning scheme will be presented 
and SPICE simulation results will be shown. Finally, we will 
deal with layout and topology considerations. 
2.1 
2. DESIGN 
Design of Basic Distributed Oscillators 
T h a t c h  
Znatch i I 
~ ~~~~ ~ 
Figure 1. Distributed oscillator. 
An integrated distributed oscillator operates in the forward-gain 
mode of a distributed amplifier (Fig. 1). The forward (to the 
right in the figure) wave on the gate line is amplified by each 
transistor. Amplified waves travel forward on the drain line in 
synchronization with the wave on the gate line and add 
constructively at each tap point on the drain line. The sum from 
the output of the drain line is then fed back to the input of the 
gate line. The forward wave on the gate line and the backward 
(to the left in the figure) wave on the drain line are absorbed by 
the matched terminations. 
Coplanar striplines (Fig. 2) are used in order to maximize the 
characteristic impedance (a), which is proportional to the open- 
loop gain and thus the oscillation amplitude. 
The design specifications are oscillation frequency and 
amplitude. The design variables are geometry (width, spacing, 
0-7803-5482-6/99/$10.00 02000 IEEE 
111-57 
and length) of transmission lines, number of sections, 
termination, transistor size, and bias current. 
Ground line 
Lamnation 
I V 
Figure 2. Coplanar stripline. 
2.2 Tuning 
Intuitively, a distributed oscillator can be tuned by varying the 
time delay of the transmission line sections. A conceptually easy 
way is to load the transmission lines with varactors so as to 
change their effective delay (Fig. 3). It can also help to balance 
the phase constants of the gate and drain lines. However, the 
quality factor, Q, of available varactors in CMOS technology is 
rather low at frequencies of interests, so that the oscillation can 
hardly start. 
Figure 3. Tuning a distributed oscillator by varactors. 
I- 
B 
Figure 4. Varying effective length of transmission lines. 
An altemative approach is to vary the length of the transmission 
,lines to tune the distributed oscillator. Since the physical length 
cannot be changed, we choose to change the effective length by 
changing the transconductance of active transistors. As can be 
seen in Figure 4, each gain section comprises of two gain 
transistors (MI, MI) which are coupled between the gate and 
drain lines. These two transistors are separated by an additional 
transmission line segment (highlighted) on the drain line, with 
both gates connected to the same point on the gate line. 'The 
sources of MI and MZ are ac grounded by two bypass capacitors, 
while dc biased by the current sources. By varying the currents, 
the total effective length of the transmission line is varied 
between its minimum and maximum. 
For instance, when 11 is maximum and 12 is zero, only MI 
contributes to amplification. Therefore, the effective length of 
the transmission lines reaches its maximum value, which is 
longer than the minimum by the length of the highlighted 
segment between MI and Mz. A voltage change at node A will 
take the longest time to reach node B. This corresponds to the 
lowest oscillation frequency. On the other hand, when 11 is zero 
and 12 is maximum, the effective length of the transmission lines 
is at its minimum value, and the transmission from A to B i:; the 
fastest. Then the highest oscillation frequency is obtained. 
Tuning can be achieved by distributing the current with 
different ratio between the two sets of transistors, and thus 
adding the output signals from the gain transistors in different 
phases. Therefore, the effective total length of the transmission 
lines lies between the maximum and minimum, and the 
oscillation frequency can be tuned continuously. The tuning , 
range is determined by the ratio of the length of the transmi:;sion ; 
line segment between MI and M2 in each section to the total 
length of the transmission lines, and therefore can be adjusted 
based on the application. We will refer to this techniqu.e as 
Current Steering Tuning. 
The problem with current steering is delay mismatch. The 
traveling wave on the gate.and drain lines will experience a 
phase mismatch, which depends on the relative current in MI  
and M2. Also, the loading effect due to the transistor capacitance 
is more severe on the gate line than the drain line, since the gate 
capacitance of both gain transistors are connected to the same 
tapping point on the gate line while the drain capacitances are 
separated. The introduced phase mismatch degrades the 
oscillation amplitude or can even stop the oscillation. In order to 
balance the delay, a complementary configuration is devised 
(Fig. 5) .  It is different from the former one in that the gain 
transistors are separated by an additional transmission line 
segment on the gate line while driving the same node on the 
drain line. A pair of these complementary sections can be used 
to cancel the delay mismatch to the first order. We will refer to 
this delay balancing technique as Current-Steering Delay- 
Balanced Tuning. 
eg 5. 
Figure 5. Complementary configuration for delay 
balancing. 
In-58 
The complete structure of a four-section DVCO with this 
technique is shown in Fig. 6a. It comprises of two gate-line- 
tuning (GLT) sections (Fig. 6b) and two drain-line-tuning 
(DLT) sections (Fig. 6c) to compensate the delay mismatch. For 
the convenience of layout, the four sections are in the sequence 
of GLT-GLT-DLT-DLT. In each section, 11 and IZ are replaced 
with the current source M5 and two current steering transistors 
(M3, M4). The differential control voltage steers the tail current 
between MI and M2. Bypass capacitors CSI and CSZ guarantee 
that sources of MI and MZ are ac grounded for maximum gain at 
the frequency of oscillation. They also suppress potential low 
frequency common-mode oscillations by lowering the gain at 
low frequencies. 
10 35 
1030- 
1025 
10 20 - 
3 1015 - 
P O t 0 .  g 1005~ 
1000- 
9 95 - 
9 9 0 ~  
Drain Line Gate Line 
Termination 
(a) 
- 
I I 
4 > 
4 ). 
(C) 
Figure 6. Current-steering delay-balanced tuning: (a) 
block diagram of a DVCO; (b) GLT; (c) DLT. 
2.3 Simulation Results 
The DVCOs are designed in Conexant's 0.35 pm BiCMOS 
technology using only CMOS transistors [SI. The top metal layer 
is 3 pm thick, and 4 pm above the substrate. 
Circuit parameters from full-wave electromagnetic simulations 
[9] and lossy transmission line models in HSPICE are used to 
simulate coplanar striplines with a width of 3 pm (ground line 8 
pm) and spacing of 10 pn (Fig. 2). 
Figure 7a shows the startup characteristics of the designed four- 
stage CMOS DVCO. The simulated output spectrum in steady 
state can be seen in Figure 7b showing the power in the 
harmonics. The DVCO has a center frequency of 10 GHz with 
tuning span between 9.9 and 10.3 GHz (Fig. 7c). 
1.511 I 
-80 41 , , , , , , , 
0 10 20 30 
Frequency (GHz) 
(b) 
-025 0 2 0  0 1 5  0 1 0  0 0 5  000 005 010 015 
Dlffsrsntlsl Voltage (VI 
(C) 
Figure 7. Simulation results: (a) output waveform; (b) FFT 
spectrum; (b) tuning range. 
111-59 
2.4 Layout 
Due to very high frequency operation and sensitivity to effective 
length of the transmission lines, special attention should be paid 
to the layout. A few points are highlighted here: 
................. , ..............._ 
i ............... i i ............... i 
I 
................. , ..............._ 
................. i ..............., 
- 
The gate line and drain line are in parallel to maintain 
synchronization of signals on the two lines. There 
should also be enough spacing between different 
coplanar striplines to prevent interference. However, 
since there is a feedback loop in the whole transmission 
line structure, a crossing where one transmission line 
goes underneath the other is inevitable. 
There are reverse-biased PN junctions (laminations) 
underneath the transmission lines to terminate Eddy 
currents to lower the loss of the transmission lines. 
In each section, the two gain transistors have identical 
distance from the tapping points on the transmission 
lines in order not to introduce unbalanced excess delay. 
The dc bias lines are perpendicular to the transmission 
lines to minimize the capacitive loading on the 
transmission lines. 
The output and terminations are easily accessible from 
the pad frame. To be able to use microwave coplanar 
probes, there should be only one RF pad (totally three) 
on each side of the chip, and thus all dc pads should be 
on the same side, convenient for wire-bonding. 
Figure 9. Layout of the DVCO. 
4. ACKNOWLEDGEMENT 
The authors thank Conexant Systems, Newport Beach, CA for 
chip fabrication, and especially thank Stephen Lloyd, Bljan 
Bhattacharyya, Frank In’tveld, Jie Yu and Ronald Hlavac for 
CAD support and helpful discussions on testing. We would also 
like to acknowledge Taavi Hirvonen, Lawrence Cheung and 
Scott Kee of Caltech for helpful discussions. 
5. REFERENCES 
[I] Ginzton E. L., Hewlett W. R., Jasberg J. H., and Noe I. D., 
“Distributed amplification,” Proc. IRE, vol. 36, pp. 956- 
969, Aug. 1948. 
[2] Ayasli Y., Vorhaus J. L., Mozzi R. L., Reynolds L. D., 
“Monolithic GaAs travelling-wave amplifier,” Electronics 
Letters, vol. 17, no. 12, pp. 413-414, June 1981. 
[3] Sullivan P. J., Xavier B. A., Costa D., Ku W. H., “An 
integrated CMOS distributed amplifier utilizing packaging 
inductance,” IEEE Trans. Microwave Theory Tech., vol. 
45, no. 10, pp. 1969-1976, Oct. 1997. 
[4] Ballweber B., Gupta R., Allstot D. J., “Fully-Integrated 
CMOS RF Amplifiers,” IEEE Intemational Solid-State 
Circuits Conference, San Francisco, CA, -Paper MF’ 4.4, 
Feb. 1999. 
[5] Skvor Z., Saunders S.R. and Aitchison C.S., “Novel 
Decade Electronically Tunable Microwave Oscillator based 
on the distributed amplifier,” Electronics Letters, ~01.28, 
no. 17, pp.1647-1648, Aug. 1992. 
[6] Divina L., Skvor Z., “The distributed oscillator at 4 GHz,” 
IEEE Trans. Microwave Theory Tech., vol. 46, no. 12, pp. 
2240-2243, Dec. 1998. 
[7] Kleveland B., Diaz C. H., Dieter D., Madden L., Lee T. H., 
S. S .  Wong, “Monolithic CMOS Distributed Amplifier and 
Oscillator,” ZEEE International Solid-State Circuit 
Conference, Paper MP 4.3, Feb. 1999. 
[S] Racanelli M. et al., “BC35: 0.35 pm RF BiCMOS 
Technology for Highly Integrated Wireless Systems,” ZEEe 
RFIC Symposium, Paper TUE2-3, June 1999. 
[9] Ansoft High Frequency Structure Simulator, v7.0 
111-60 


A novel tuning technique for distributed voltage controlled oscillators

An integrated CMOS distributed amplifier utilizing packaging inductance,”

Ansoft High Frequency Structure Simulator,

Distributed amplification,”

Monolithic GaAs travelling-wave amplifier,”

Novel Decade Electronically Tunable Microwave Oscillator based on the distributed amplifier,”

The distributed oscillator at 4 GHz,”

http://authors.library.caltech.edu/13079/1/HUWiscas00.pdf

A novel tuning technique for distributed voltage controlled oscillators

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