A Hybrid Folded Cascode OP Amp with Positive Feedback And DSB Circuit

A novel high-speed folded-cascode OP Amp with positive feedback and a dynamic switching bias circuit, which increases the speed and lower the power dissipation has been proposed . The proposed Op-Amp was designed in a standard 0.18µm CMOS technology and simulation is performed using tanner EDA tool. Simulation results show a considerable increase in speed, increased output voltage swing and low power consumption for the presented Op-Amp. This proposed circuit overcomes some drawbacks of the conventional circuit in which only positive feedback is used. DOI: 10.17762/ijritcc2321-8169.150610

Low Power Bio-potential Amplifier (for EEG)

The size and dependency on power supply of current biopotential data acquisition systems prohibit continuous monitoring of biopotential signals through battery powered devices. As the interest in continuous monitoring of EEG increases for healthcare and research purposes such as seizure detection, there is an increasing need to bring down the power consumption on the biopotential amplifier (BPA). BPA is one of the most power consuming components in the biopotential data acquisition system. In this FYP, we will develop a method to improve the existing BPA using MIMOS 0.35um process technology through implementation of various low power flicker noise cancelation techniques. Techniques used include low impedance node chopping and non-overlapping demodulation chopping. The scope of this FYP is focusing on design and simulation on Cadence software in circuit level implementation. This work provides insights as well as a starting point in lowering the power consumption of bio-potential data acquisition system. This will help to enable battery power system for continuous monitoring of EEG signals in the future. This final report discusses on both the literature review, background of the projects and methodology as well as the outcome of the work. The report is concluded by suggesting future works that can be carried out in this final year project (FYP)

Study of Single-Event Transient Effects on Analog Circuits

Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles can interrupt electronics operation or crash the systems. This phenomenon is particularly serious in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) since most of modern ICs are implemented with CMOS technologies. The problem is getting worse with the technology scaling down. Radiation-hardening-by-design (RHBD) is a popular method to build CMOS devices and systems meeting performance criteria in radiation environment. Single-event transient (SET) effects in digital circuits have been studied extensively in the radiation effect community. In recent years analog RHBD has been received increasing attention since analog circuits start showing the vulnerability to the SETs due to the dramatic process scaling. Analog RHBD is still in the research stage. This study is to further study the effects of SET on analog CMOS circuits and introduces cost-effective RHBD approaches to mitigate these effects. The analog circuits concerned in this study include operational amplifiers (op amps), comparators, voltage-controlled oscillators (VCOs), and phase-locked loops (PLLs). Op amp is used to study SET effects on signal amplitude while the comparator, the VCO, and the PLL are used to study SET effects on signal state during transition time. In this work, approaches based on multi-level from transistor, circuit, to system are presented to mitigate the SET effects on the aforementioned circuits. Specifically, RHBD approach based on the circuit level, such as the op amp, adapts the auto-zeroing cancellation technique. The RHBD comparator implemented with dual-well and triple-well is studied and compared at the transistor level. SET effects are mitigated in a LC-tank oscillator by inserting a decoupling resistor. The RHBD PLL is implemented on the system level using triple modular redundancy (TMR) approach. It demonstrates that RHBD at multi-level can be cost-effective to mitigate the SEEs in analog circuits. In addition, SETs detection approaches are provided in this dissertation so that various mitigation approaches can be implemented more effectively. Performances and effectiveness of the proposed RHBD are validated through SPICE simulations on the schematic and pulsed-laser experiments on the fabricated circuits. The proposed and tested RHBD techniques can be applied to other relevant analog circuits in the industry to achieve radiation-tolerance

Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies

Amplifier Design for a Pipeline ADC in 90nm Technology

This paper explains the choices taken for the design of two full differential operational amplifiers. These op amp have been designed for the third and the fifth stage of a pipelined A/D Converter. It shows also the solutions found to reach high gain, wide bandwidth and short settling time, without degrading too much the output swing. First the operational amplifier specification are extracted starting from the ADC architecture, then the issues related to the sub-micrometrical design are analysed; the different structures tested are then presented and the motivation of the final topology choice are shown. It presents then the op amp schematic implementation, the simulation results and the layout with the 90nm TSMC design ki

A Silicon Carbide Power Management Solution for High Temperature Applications

The increasing demand for discrete power devices capable of operating in high temperature and high voltage applications has spurred on the research of semiconductor materials with the potential of breaking through the limitations of traditional silicon. Gallium nitride (GaN) and silicon carbide (SiC), both of which are wide bandgap materials, have garnered the attention of researchers and gradually gained market share. Although these wide bandgap power devices enable more ambitious commercial applications compared to their silicon-based counterparts, reaching their potential is contingent upon developing integrated circuits (ICs) capable of operating in similar environments. The foundation of any electrical system is the ability to efficiently condition and supply power. The work presented in this thesis explores integrated SiC power management solutions in the form of linear regulators and switched capacitor converters. While switched-mode converters provide high efficiency, the requirement of an inductor hinders the development of a compact, integrated solution that can endure harsh operating environments. Although the primary research motivation for wide bandgap ICs has been to provide control and protection circuitry for power devices, the circuitry designed in this work can be incorporated in stand-alone applications as well. Battery or generator powered data acquisition systems targeted towards monitoring industrial machinery is one potential usage scenario

Low Power Bio-potential Amplifier (for EEG)

The size and dependency on power supply of current biopotential data acquisition systems prohibit continuous monitoring of biopotential signals through battery powered devices. As the interest in continuous monitoring of EEG increases for healthcare and research purposes such as seizure detection, there is an increasing need to bring down the power consumption on the biopotential amplifier (BPA). BPA is one of the most power consuming components in the biopotential data acquisition system. In this FYP, we will develop a method to improve the existing BPA using MIMOS 0.35um process technology through implementation of various low power flicker noise cancelation techniques. Techniques used include low impedance node chopping and non-overlapping demodulation chopping. The scope of this FYP is focusing on design and simulation on Cadence software in circuit level implementation. This work provides insights as well as a starting point in lowering the power consumption of bio-potential data acquisition system. This will help to enable battery power system for continuous monitoring of EEG signals in the future. This final report discusses on both the literature review, background of the projects and methodology as well as the outcome of the work. The report is concluded by suggesting future works that can be carried out in this final year project (FYP)

Design and Assembly of High-Temperature Signal Conditioning System on LTCC with Silicon Carbide CMOS Circuits

The objective of the work described in this dissertation paper is to develop a prototype electronic module on a low-temperature co-fired ceramic (LTCC) material. The electronic module would perform signal conditioning of sensor signals (thermocouples) operating under extreme conditions for applications like gas turbines to collect data on the health of the turbine blades during operation so that the turbines do not require shutdown for inspection to determine if maintenance is required. The collected data can indicate when such shutdowns, which cost $1M per day, should be scheduled and maintenance actually performed. The circuits for the signal conditioning system within the prototype module must survive the extreme temperature, pressure, and centrifugal force, or G-force, present in these settings. Multiple fabrication runs on different integrated silicon carbide (SiC) process technologies have been carried out to meet the system requirements. The key circuits described in this dissertation are - two-stage op amp topologies and voltage reference, which are designed and fabricated in a new SiC CMOS process. The SiC two-stage op amp with PFET differential input pair showed 48.9 dB of DC gain at 500oC. The voltage reference is the first in SiC CMOS technology to employ an op amp-based topology. The op amp circuit in the voltage reference is a two-stage with NFET differential input pair that uses the indirect compensation technique for the first time in the SiC CMOS process to provide 42.5 dB gain at 350oC. The designed prototype module implemented with these circuits was verified to provide signal conditioning and signal transmission at 300oC. The signal transmission circuit on the module was also verified to operate with a resonant inductive wireless power transfer method at a frequency of 11.8 MHz for the first time. A second prototype module was also developed with the previously fabricated 1.2 µm SiC CMOS process. The second module was successfully tested (with wired power supply) to operate at 440oC inside a probe-station and also verified for the first time to sustain signal transmission (34.65 MHz) capability inside a spin-rig at a rotational speed of 10,920 rpm. All designed modules have dimensions of (length) 68.5 mm by (width) 34.3 mm to conform to the physical size requirements of the gas turbine blade