Optimal design of a 2.4 GHz CMOS low noise amplifier

In most RF receivers, the Low Noise Amplifier (LNA) is normally the first component, whose performance is very critical. For the LNA architecture that uses source degeneration inductors and cascode topology, the performance depends largely on the performance of the inductors. All the parasitics associated with the inductors should be thoroughly analyzed and taken into consideration while designing the LNA. The work presented in this thesis can be broadly classified as follows: optimization of the LNA design with respect to all the parasitics associated with the on-chip spiral inductors, modeling high performance inductors, which are embedded in the silicon substrate and analysis of parasitic effects from the Electro Static Discharge (ESD) protection circuitry on the performance of the LNA. A methodology has been developed such that the LNA design can be optimized in the presence of an ESD protection circuitry in order to achieve the required input impedance match. This optimization procedure is presented for all possible placements of the ESD protection circuitry at the input of the LNA, that is, with respect to the gate inductor being realized on-chip or off-chip or a combination of on-chip and off-chip inductors. The thesis presents the procedure to vary the source inductance and gate inductance values in the presence of parasitic ESD capacitance in order to optimize LNA design such that the required input impedance match is maintained

Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA) based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology

An Electrostatic Discharge (ESD) protected Low- Noise Amplifier (LNA) for the 2.4 GHz ISM band designed in a 0.13 mum standard RFCMOS technology is presented. The amplifier, including packaging effects, achieves 16.8 dB power gain, reflexion coefficients S 11 , S 22 < -30 dB over the 2.4 GHz ISM band, a peak noise figure of 1.8 dB, and an IIP 3 of 1 dBm, while drawing less than 4.5 mA dc biasing current from the 1.2 V power supply. Further, the LNA withstands a Human Body Model (HBM) ESD stress up to plusmn2.0 kV, by means of the additional custom protection circuitry.Comisión Interministerial de Ciencia y Tecnología TIC2003-02355Ministerio de Educación y Ciencia TEC2006-0302

CMOS RF low noise amplifier with high ESD immunity.

Tang Siu Kei.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 107-111).Abstracts in English and Chinese.Acknowledgements --- p.iiAbstract --- p.iiiList of Figures --- p.xiList of Tables --- p.xviChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview of Electrostatic Discharge --- p.1Chapter 1.1.1 --- Classification of Electrostatic Discharge Models --- p.1Chapter 1.2 --- Electrostatic Discharge in CMOS RF Circuits --- p.4Chapter 1.3 --- Research Goal and Contribution --- p.6Chapter 1.4 --- Thesis Outline --- p.6Chapter Chapter 2 --- Performance Parameters of Amplifier --- p.8Chapter 2.1 --- Amplifier Gain --- p.8Chapter 2.2 --- Noise Factor --- p.9Chapter 2.3 --- Linearity --- p.11Chapter 2.3.1 --- 1-dB Compression Point --- p.13Chapter 2.3.2 --- Third-Order Intercept Point --- p.14Chapter 2.4 --- Return Loss --- p.16Chapter 2.5 --- Power Consumption --- p.18Chapter 2.6 --- HBM ESD Withstand Voltage --- p.19Chapter Chapter 3 --- ESD Protection Methodology for Low Noise Amplifier --- p.21Chapter 3.1 --- Dual-Diode Circuitry --- p.22Chapter 3.1.1 --- Working Principle --- p.22Chapter 3.1.2 --- Drawbacks --- p.24Chapter 3.2 --- Shunt-Inductor Method --- p.25Chapter 3.2.1 --- Working Principle --- p.25Chapter 3.2.2 --- Drawbacks --- p.27Chapter 3.3 --- Common-Gate Input Stage Method --- p.28Chapter 3.3.1 --- Built-in ESD Protecting Mechanism --- p.29Chapter 3.3.2 --- Competitiveness --- p.31Chapter Chapter 4 --- Design Theory of Low Noise Amplifier --- p.32Chapter 4.1 --- Small-Signal Modeling --- p.33Chapter 4.2 --- Method of Input Termination --- p.33Chapter 4.2.1 --- Resistive Termination --- p.34Chapter 4.2.2 --- Shunt-Series Feedback --- p.34Chapter 4.2.3 --- l/gm Termination --- p.35Chapter 4.2.4 --- Inductive Source Degeneration --- p.36Chapter 4.3 --- Method of Gain Enhancement --- p.38Chapter 4.3.1 --- Tuned Amplifier --- p.38Chapter 4.3.2 --- Multistage Amplifier --- p.40Chapter 4.4 --- Improvement of Reverse Isolation --- p.41Chapter 4.4.1 --- Common-Gate Amplifier --- p.41Chapter 4.4.2 --- Cascoded Amplifier --- p.42Chapter Chapter 5 --- Noise Analysis of Low Noise Amplifier --- p.44Chapter 5.1 --- Noise Sources of MOS Transistor --- p.44Chapter 5.2 --- Noise Calculation using Noisy Two-Port Network --- p.46Chapter 5.3 --- Noise Calculation using Small-Signal Model --- p.49Chapter 5.3.1 --- Low Noise Amplifier with Inductive Source Degeneration --- p.49Chapter 5.3.2 --- Common-Gate Low Noise Amplifier --- p.52Chapter Chapter 6 --- Design of an ESD-protected CMOS Low Noise Amplifier --- p.54Chapter 6.1 --- Design of DC Biasing Circuitry --- p.55Chapter 6.2 --- Design of Two-Stage Architecture --- p.57Chapter 8.3.1 --- Design of Common-Gate Input Stage --- p.57Chapter 8.3.2 --- Design of Second-Stage Amplifier --- p.59Chapter 6.3 --- Stability Consideration --- p.61Chapter 6.4 --- Design of Matching Networks --- p.62Chapter 6.4.1 --- Design of Inter-Stage Matching Network --- p.64Chapter 6.4.2 --- Design of Input and Output Matching Networks --- p.67Chapter Chapter 7 --- Layout Considerations --- p.70Chapter 7.1 --- MOS Transistor --- p.70Chapter 7.2 --- Capacitor --- p.72Chapter 7.3 --- Spiral Inductor --- p.74Chapter 7.4 --- Layout of the Proposed Low Noise Amplifier --- p.76Chapter 7.5 --- Layout of the Common-Source Low Noise Amplifier --- p.79Chapter 7.6 --- Comparison between Schematic and Post-Layout Simulation Results --- p.81Chapter Chapter 8 --- Measurement Results --- p.82Chapter 8.1 --- Experimental Setup --- p.82Chapter 8.1.1 --- Testing Circuit Board --- p.83Chapter 8.1.2 --- Experimental Setup for s-parameter --- p.84Chapter 8.1.3 --- Experimental Setup for Noise Figure --- p.84Chapter 8.1.4 --- Experimental Setup for 1-dB Compression Point --- p.85Chapter 8.1.5 --- Experimental Setup for Third-Order Intercept Point --- p.86Chapter 8.1.6 --- Setup for HBM ESD Test --- p.87Chapter 8.2 --- Measurement Results of the Proposed Low Noise Amplifier --- p.89Chapter 8.2.1 --- S-parameter Measurement --- p.90Chapter 8.2.2 --- Noise Figure Measurement --- p.91Chapter 8.2.3 --- Measurement of 1-dB Compression Point --- p.92Chapter 8.2.4 --- Measurement of Third-Order Intercept Point --- p.93Chapter 8.2.5 --- HBM ESD Test --- p.94Chapter 8.2.6 --- Summary of Measurement Results --- p.95Chapter 8.3 --- Measurement Results of the Common-Source Low Noise Amplifier --- p.96Chapter 8.3.1 --- s-parameter Measurement --- p.97Chapter 8.3.2 --- Noise Figure Measurement --- p.98Chapter 8.3.3 --- Measurement of 1-dB Compression Point --- p.99Chapter 8.3.4 --- Measurement of Third-Order Intercept Point --- p.100Chapter 8.3.5 --- HBM ESD Test --- p.101Chapter 8.3.6 --- Summary of Measurement Results --- p.102Chapter 8.4 --- Performance Comparison between Different Low Noise Amplifier Designs --- p.103Chapter Chapter 9 --- Conclusion and Future Work --- p.105Chapter 9.1 --- Conclusion --- p.105Chapter 9.2 --- Future Work --- p.106References --- p.107Author's Publications --- p.11

A low-power RF front-end for 2.5 GHz receivers

© 2008 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a low power and low cost front end for a direct conversion 2.5 GHz ISM band receiver composed of a 16 kV HBM ESD protected LNA, differential Gilbert-cell mixers, and high-pass filters for DC offset cancellation. The whole front-end is implemented in a 2P6M 0.18 µm RFCMOS process. It exhibits a voltage gain of 24dB and a SSB noise figure of 8.4dB which make it suitable for most of the 2.5 GHz wireless short-range communication transceivers. The achieved power consumption is only 1.06mW from a 1.2V power supply.Peer ReviewedPostprint (published version

Analysis and design of a high power millimeter-wave power amplifier in a SiGe BiCMOS technology

Our current society is characterized by an ever increasing need for bandwidth leading towards the exploration of new parts of the electromagnetic spectrum for data transmission. This results in a rising interest and development of millimeter-wave (mm-wave) circuits which hold the promise of short range multi-gigabit wireless transmissions at 60GHz. These relatively new applications are to co-exist with more established mm-wave consumer products including satellite systems in the Ka-band (26.5GHz - 40GHz) allowing e.g.: video broadcasting, voice over IP (VoIP), internet acces to remote areas, ... Both need significant linear power amplification due to the high attenuation typical for this part of the spectrum, however, satellite systems demand a saturated output power which is easily an order of magnitude larger (output powers in excess of 30dBm / 1W). Monolithic microwave integrated circuits (MMICs) employing III-V chip technologies, e.g.: gallium arsenide (GaAs), gallium nitride (GaN), have historically been the preferred choice to implement efficient mm-wave power amplifiers (PA) with a high saturated output power (>30dBm). To further increase the commercial viability of consumer products in this market segment a low manufacturing cost for the power amplifier, together with the possible integration of additional functions, is highly desirable. These features are the strongpoint of silicon based chip technologies like CMOS and SiGe BiCMOS. However, these technologies have a breakdown voltage typically below 2V for nodes capable of millimeter-wave applications while III-V transistors with equivalent frequency performance demonstrate breakdown voltages in excess of 8V. Because of this, output powers of CMOS and SiGe BiCMOS Ka-band power amplifiers rarely exceed 20dBm which poses the main hurdle for using these technologies in satellite communication (SATCOM). To overcome the limited output power of a single amplifying cell in a silicon technology, caused by the low breakdown voltage, multiple power amplifiers cells need to have their output power effectively combined on-chip. This requires the on-chip integration of high-Q passives within a relative small area to realize both the impedance transformation, to create the optimal load impedance for the different amplifier cells, and implement an efficient on-chip power combination network. Compared to III-V technologies this is again a challenge due to the use of a silicon substrate which introduces higher losses. Once a large enough on-chip output power is created, the issue of launching this signal to the outside world remains. Moreover, due to the limited efficiency of mm-wave PAs, the generated on-chip heat will increase when larger output power are required. This means a chipto-board interface with a low thermal resistance and a low loss electrical connection needs to be devised. Proof of the viability of silicon as a serious candidate for the integration of medium and high power Ka-band amplifiers will only be delivered by long term research and the actual creation of such an amplifier. In this context, the initial goal for the presented work is proposed. This consists of the creation of a power amplifier with a saturated output power above 24dBm (preferably 27dBm), a gain larger than 20dB and an efficiency in excess of 10% (preferably 15%). These specifications where conceived with the precondition of using a 250nm SiGe BiCMOS technology (IHP’s SG25H3) with an fT of 110GHz and a collector to emitter breakdown voltage in open base conditions (BVCEO) of 2.3V. The use of this technology is a significant challenge due to the limited speed, rule of thumb is to have at least one fifth of the fT as the operating frequency, which reflects in the attainable power added efficiency (PAE). On the other hand, proving the possible implementation in this “older” technology shows great potential towards the future integration in a fast technology (e.g.: IHP’s SG13G2, ft =300GHz). Next to issues caused by limitations of the chip technology, the proposed specifications allows to identify generic difficulties with high power silicon PA design, e.g.: design of efficient on-chip power combiners, thermal management, single-ended to differential conversion, ... As this work is of an academic nature the intention of this design was to leave the beaten track and explore alternative topologies. This has led to the adoption of a driver stage using translinear loops for biasing and a transformer-type Wilkinson power combiner previously only used in cable television (CATV) applications. Although the power combiner showed 2dB more loss than expected due to higher than expected substrate losses, both topologies show promise for further integration. Furthermore, an in-depth analysis was performed on the output stage which uses positive feedback to increase its gain. The entire design consists of a four-way power combining class AB power amplifier together with test structures of which the performance was verified by means of probing. Due to the previously mentioned higher than expected loss in the on-chip power combiner, the total output power and power added efficiency (PAE) was 2dB lower than expected from simulations. The result is a saturated output power at 32GHz of 24.1dBm with a PAE of 7.2% and a small signal gain of 25dB. This demonstrates the capability of SiGe BiCMOS to implement PA’s for medium-power mm-wave applications. Moreover, to the best of the author’s knowledge, this PA achieves the second highest saturated output power when comparing SiGe BiCMOS PA’s with center frequency in or close to the Ka-band. The 1dB compression point of this amplifier lies at 22.7dBm which is close to saturated output power and results in a low spectral regrowth when compared to commercial GaAs PA’s (compared with 2MBaud 16QAM input signal at 10dB back-off). Many possible improvements to this design remain. The most important would be the re-design of the on-chip power combiner, possibly with a floating ground shield, to reduce the losses and increase the total output power and PAE. Also the porting of the design to a faster chip technology might result in a considerable increase of the output stage efficiency at the cost of needing to combine more amplifier cells. The transition to a faster chip technology would additionally allow to use this design for alternative mm-wave applications like automotive radar at 79GHz andWiGig at 60GHz