Design of Digital Frequency Synthesizer for 5G SDR Systems

The previous frequency synthesizer techniques for scalable SDR are not compatible with high end applications due to its complex computations and the intolerance over increased path interference rate which leads to an unsatisfied performance with improved user rate in real time environment. Designing an efficient frequency synthesizer framework in the SDR system is essential for 5G wireless communication systems with improved Quality of service (QoS). Consequently, this research has been performed based on the merits of fully digitalized frequency synthesizer and its explosion in wide range of frequency band generations. In this paper hardware optimized reconfigurable digital base band processing and frequency synthesizer model is proposed without making any design complexity trade-off to deal with the multiple standards. Here fully digitalized frequency synthesizer is introduced using simplified delay units to reduce the design complexity. Experimental results and comparative analyzes are carried out to validate the performance metrics and exhaustive test bench simulation is also carried out to verify the functionality

Transceiver architectures and sub-mW fast frequency-hopping synthesizers for ultra-low power WSNs

Wireless sensor networks (WSN) have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. This revolution will finally connect together the physical world of the human and the virtual world of the electronic devices. Though in the recent years large progress in power consumption reduction has been made in the wireless arena in order to increase the battery life, this is still not enough to achieve a wide adoption of this technology. Indeed, while nowadays consumers are used to charge batteries in laptops, mobile phones and other high-tech products, this operation becomes infeasible when scaled up to large industrial, enterprise or home networks composed of thousands of wireless nodes. Wireless sensor networks come as a new way to connect electronic equipments reducing, in this way, the costs associated with the installation and maintenance of large wired networks. To accomplish this task, it is necessary to reduce the energy consumption of the wireless node to a point where energy harvesting becomes feasible and the node energy autonomy exceeds the life time of the wireless node itself. This thesis focuses on the radio design, which is the backbone of any wireless node. A common approach to radio design for WSNs is to start from a very simple radio (like an RFID) adding more functionalities up to the point in which the power budget is reached. In this way, the robustness of the wireless link is traded off for power reducing the range of applications that can draw benefit form a WSN. In this thesis, we propose a novel approach to the radio design for WSNs. We started from a proven architecture like Bluetooth, and progressively we removed all the functionalities that are not required for WSNs. The robustness of the wireless link is guaranteed by using a fast frequency hopping spread spectrum technique while the power budget is achieved by optimizing the radio architecture and the frequency hopping synthesizer Two different radio architectures and a novel fast frequency hopping synthesizer are proposed that cover the large space of applications for WSNs. The two architectures make use of the peculiarities of each scenario and, together with a novel fast frequency hopping synthesizer, proved that spread spectrum techniques can be used also in severely power constrained scenarios like WSNs. This solution opens a new window toward a radio design, which ultimately trades off flexibility, rather than robustness, for power consumption. In this way, we broadened the range of applications for WSNs to areas in which security and reliability of the communication link are mandatory

Design and Implementation of an RF Front-End for Software Defined Radios

Software Defined Radios have brought a major reformation in the design standards for radios, in which a large portion of the functionality is implemented through pro­ grammable signal processing devices, giving the radio the ability to change its op­ erating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency and other analog components of the traditional radios and emphasizes digital signal processing to enhance overall receiver flexibility. Field Programmable Gate Arrays (FPGA) are a suitable technology for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability. Software defined radio is a very broad field, encompassing the design of various technologies all the way from the antenna to RF, IF, and baseband digital design. The RF section primarily consists of analog hardware modules. The IF and baseband sections are primarily digital. It is the general process of the radio to convert the incoming signal from RF to IF and then IF to baseband for better signal processing system. In this thesis, some of major building blocks of a Software defined radio are de­ signed and implemented using FPGAs. The design of a Digital front end, which provides the bridge between the baseband and analog RF portions of a wireless receiver, is synthesized. The Digital front end receiver consists of a digital down converter(DDC) which in turn comprises of a direct digital frequency synthesizer (DDFS), a phase accumulator and a low pass filter. The signal processing block of the DDFS is executed using Co-ordinate Rotation Digital Computer (CORDIC) iii Abstract algorithm. Cascaded-Integrator-Comb filters (CIC) are implemented for changing the sample rate of the incoming data. Application of a DDC includes software ra­ dios, multicarrier, multimode digital receivers, micro and pico cell systems,broadband data applications, instrumentation and test equipment and in-building wireless tele­ phony. Also, in this thesis, interfaces for connecting Texas Instruments high speed and high resolution Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) with Xilinx Virtex-5 FPGAs are also implemented and demonstrated

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

77-GHz Waveform Generator with Multiple Frequency Shift Keying for Multi-target Detection Automotive Radar Applications

Department of Electrical EngineeringIn automotive radar applications, the modulation waveform plays an important role in detecting multiple targets. Two well-known continuous waves in the literature are Frequency Modulated Continuous Wave (FMCW) and Frequency Shift Keying (FSK). These two waveforms basically ful l the requirements of automotive radars. However, two modulations have limitations in multiple target situations. The ghost targets are introduced in FMCW radars, thus two or more measurement cycles are expanded to resolve the target ambiguities. In contrast to that FSK cannot solve targets in range direction. For this reason, the combination of FMCW and FSK was proposed, called MFSK. This waveform shows good performance, with a high range and velocity resolution, short measurement time, and ability to avoid ghost targets. The main drawback of this modulation is the complexity. In this thesis, all the perspectives about MFSK modulation waveform from basic fundamentals to hardware implementation are presented. In addition, the proposed MFSK waveform generator for automotive radar system is elaborated to improve the target detections and shorter measurement time.. . .ope

High performance continuous-time filters for information transfer systems

Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications

Tutorial on direct digital synthesizer structure improvements and static timing analysis

The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have been rapidly developed. Because of FPGAs’ high speed, high integration and field-programmable advantages, the devices are widely used in digital processing and are increasingly favored by hardware circuit design engineers. FPGAs also provide a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such high-speed switching, fine tunability and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate some ways to optimize the DDS structure to save hardware resources and increase chip speed without sacrificing signal quality. The Verilog hardware description language is used as the development language. This thesis will describe entire designs of both DDS with traditional structure and DDS with new structures. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality

비디오 클럭 주파수 보상 구조를 이용한 디스플레이포트 수신단 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 정덕균.This thesis presents the design of DisplayPort receiver which is a high speed digital display interface replacing existing interfaces such as DVI, HDMI, LVDS and so on. The two prototype chips are fabricated, one is a 5.4/2.7/1.62-Gb/s multi-rate DisplayPort receiver and the other is a 2.7/1.62-Gb/s multi-rate Embedded DisplayPort (eDP) receiver for an intra-panel display interface. The first receiver which is designed to support the external box-to-box display connection provides up to 4K resolution (4096×2160) with the maximum data rate of 21.6 Gb/s when 4 lanes are all used. The second one aims to connect internal chip-to-chip connection such as graphic processors to display panels in notebooks or tablet PCs. It supports the maximum data rate of 10.8 Gb/s with 4-lane operation which is able to provide the resolution of WQXGA (2560×1600). Since there is no dedicated clock channel, it must contain clock and data recovery (CDR) circuit to extract the link clock from the data stream. All-Digital CDR (ADCDR) is adopted for area efficiency and better performances of the multi-rate operation. The link rate is fixed but the video clock frequency range is fairly wide for supporting all display resolutions and frame rates. Thus, the wide range video clock frequency synthesizer is essential for reconstructing the transmitted video data. A source device starts link training before transmitting video data to recover the clock and establish the link. When the loss of synchronization between the source device and the sink device happens, it usually restarts the link training and try to re-establish the link. Since link training spends several milliseconds for initializing, the video image is not displayed properly in the sink device during this interval. The proposed clock recovery scheme can significantly shorten the time to recover from the link failure with the ADCDR topology. Once the link is established after link training, the ADCDR memorizes the DCO codes of the synchronization state and when the loss of synchronization happens, it restores the previous DCO code so that the clock is quickly recovered from the failure state without the link re-training. The direct all-digital frequency synthesizer is proposed to generate the cycle-accurate video clock frequency. The video clock frequency has wide range to cover all display formats and is determined by the division ratio of large M and N values. The proposed frequency synthesizer using a programmable integer divider and a multi-phase switching fractional divider with the delta-sigma modulation exhibits better performances and reduces the design complexity operating with the existing clock from the ADCDR circuit. In asynchronous clock system, the transmitted M value which changes over time is measured by using a counter running with the long reference period (N cycles) and updated once per blank period. Thus, the transmitted M is not accurate due to its low update rate, transport latency and quantization error. The proposed frequency error compensation scheme resolves these problems by monitoring the status of FIFO between the clock domains. The first prototype chip is fabricated in a 65-nm CMOS process and the physical layer occupies 1.39 mm2 and the estimated area of the link layer is 2.26 mm2. The physical layer dissipates 86/101/116 mW at 1.62/2.7/5.4 Gb/s data rate with all 4-lane operation. The power consumption of the link layer is 107/145/167 mW at 1.62/2.7/5.4 Gb/s. The second prototype chip, fabricated in a 0.13μm CMOS process, presents the physical layer area of 1.59 mm2 and the link layer area of 3.01 mm2. The physical layer dissipates 21 mW at 1.62 Gb/s and 29 mW at 2.7 Gb/s with 2-lane operation. The power consumption of the link layer is 31 mW at 1.62 Gb/s and 41 mW at 2.7 Gb/s with 2-lane operation. The core area of the video clock synthesizer occupies 0.04 mm2 and the power dissipation is 5.5 mW at a low bit rate and 9.1 mW at a high bit rate. The output frequency range is 25 to 330 MHz.ABSTRACT I CONTENTS IV LIST OF FIGURES VII LIST OF TABLES XII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 MOTIVATION 4 1.3 THESIS ORGANIZATION 12 CHAPTER 2 DIGITAL DISPLAY INTERFACE 13 2.1 OVERVIEW 13 2.2 DISPLAYPORT INTERFACE CHARACTERISTICS 18 2.2.1 DISPLAYPORT VERSION 1.2 18 2.2.2 EMBEDDED DISPLAYPORT VERSION 1.2 21 2.3 DISPLAYPORT INTERFACE ARCHITECTURE 23 2.3.1 LAYERED ARCHITECTURE 23 2.3.2 MAIN STREAM PROTOCOL 27 2.3.3 INITIALIZATION AND LINK TRAINING 30 2.3.3 VIDEO STREAM CLOCK RECOVERY 35 CHAPTER 3 DESIGN OF DISPLAYPORT RECEIVER 39 3.1 OVERVIEW 39 3.2 PHYSICAL LAYER 43 3.3 LINK LAYER 55 3.3.1 OVERALL ARCHITECTURE 55 3.3.2 AUX CHANNEL 58 3.3.3 VIDEO TIMING GENERATION 61 3.3.4 CONTENT PROTECTION 63 3.3.5 AUDIO TRANSMISSION 66 3.4 EXPERIMENTAL RESULTS 68 CHAPTER 4 DESIGN OF EMBEDDED DISPLAYPORT RECEIVER 81 4.1 OVERVIEW 81 4.2 PHYSICAL LAYER 84 4.3 LINK LAYER 88 4.3.1 OVERALL ARCHITECTURE 88 4.3.2 MAIN LINK STREAM 90 4.3.3 CONTENT PROTECTION 93 4.4 PROPOSED CLOCK RECOVERY SCHEME 94 4.5 EXPERIMENTAL RESULTS 100 CHAPTER 5 PROPOSED VIDEO CLOCK SYNTHESIZER AND FREQUENCY CONTROL SCHEME 113 5.1 MOTIVATION 113 5.2 PROPOSED VIDEO CLOCK SYNTHESIZER 115 5.3 BUILDING BLOCKS 121 5.4 FREQUENCY ERROR COMPENSATION 126 5.5 EXPERIMENTAL RESULTS 131 CHAPTER 6 CONCLUSION 138 BIBLIOGRAPHY 141 초 록 152Docto

Characterisation of MIMO radio propagation channels

Due to the incessant requirement for higher performance radio systems, wireless designers have been constantly seeking ways to improve spectrum efficiency, link reliability, service quality, and radio network coverage. During the past few years, space-time technology which employs multiple antennas along with suitable signalling schemes and receiver architectures has been seen as a powerful tool for the implementation of the aforementioned requirements. In particular, the concept of communications via Multiple-Input Multiple-Output (MIMO) links has emerged as one of the major contending ideas for next generation ad-hoc and cellular systems. This is inherently due to the capacities expected when multiple antennas are employed at both ends of the radio link. Such a mobile radio propagation channel constitutes a MIMO system. Multiple antenna technologies and in particular MIMO signalling are envisaged for a number of standards such as the next generation of Wireless Local Area Network (WLAN) technology known as 802.1 ln and the development of the Worldwide Interoperability for Microwave Access (WiMAX) project, such as the 802.16e. For the efficient design, performance evaluation and deployment of such multiple antenna (space-time) systems, it becomes increasingly important to understand the characteristics of the spatial radio channel. This criterion has led to the development of new sounding systems, which can measure both spatial and temporal channel information. In this thesis, a novel semi-sequential wideband MIMO sounder is presented, which is suitable for high-resolution radio channel measurements. The sounder produces a frequency modulated continuous wave (FMCW) or chirp signal with variable bandwidth, centre frequency and waveform repetition rate. It has programmable bandwidth up to 300 MHz and waveform repetition rates up to 300 Hz, and could be used to measure conventional high- resolution delay/Doppler information as well as spatial channel information such as Direction of Arrival (DOA) and Direction of Departure (DOD). Notably the knowledge of the angular information at the link ends could be used to properly design and develop systems such as smart antennas. This thesis examines the theory of multiple antenna propagation channels, the sounding architecture required for the measurement of such spatial channel information and the signal processing which is used to quantify and analyse such measurement data. Over 700 measurement files were collected corresponding to over 175,000 impulse responses with different sounder and antenna array configurations. These included measurements in the Universal Mobile Telecommunication Systems Frequency Division Duplex (UMTS-FDD) uplink band, the 2.25 GHz and 5.8 GHz bands allocated for studio broadcast MIMO video links, and the 2.4 GHz and 5.8 GHz ISM bands allocated for Wireless Local Area Network (WLAN) activity as well as for a wide range of future systems defined in the WiMAX project. The measurements were collected predominantly for indoor and some outdoor multiple antenna channels using sounding signals with 60 MHz, 96 MHz and 240 MHz bandwidth. A wide range of different MIMO antenna array configurations are examined in this thesis with varying space, time and frequency resolutions. Measurements can be generally subdivided into three main categories, namely measurements at different locations in the environment (static), measurements while moving at regular intervals step by step (spatial), and measurements while the receiver (or transmitter) is on the move (dynamic). High-scattering as well as time-varying MIMO channels are examined for different antenna array structures

On-Chip Analog Circuit Design Using Built-In Self-Test and an Integrated Multi-Dimensional Optimization Platform

Nowadays, the rapid development of system-on-chip (SoC) market introduces tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC fabrication process is scaling down to allow higher density of integration but makes the chips more sensitive to the process-voltage-temperature (PVT) variations. A successful IC product not only imposes great pressure on the IC designers, who have to handle wider variations and enforce more design margins, but also challenges the test procedure, leading to more check points and longer test time. To relax the designers’ burden and reduce the cost of testing, it is valuable to make the IC chips able to test and tune itself to some extent. In this dissertation, a fully integrated in-situ design validation and optimization (VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test (BIST) techniques for analog circuits. Based on the data collected from BIST, the error between the measured and the desired performance of the target circuit is evaluated using a cost function. A digital multi-dimensional optimization engine is implemented to adaptively adjust the analog circuit parameters, seeking the minimum value of the cost function and achieving the desired performance. To verify this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip. Apart from the VO system, several improved BIST techniques are also proposed in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration. Moreover, an on-chip RF receiver linearity BIST methodology for continuous and discrete-time hybrid baseband chain is proposed. The proposed receiver chain implements a charge-domain FIR filter to notch the two excitation signals but expose the third order intermodulation (IM3) tones. It simplifies the linearity measurement procedure–using a power detector is enough to analyze the receiver’s linearity. Finally, a low cost fully digital built-in analog tester for linear-time-invariant (LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to measure the delays corresponded to a ramp excitation signal and is able to estimate the pole or zero locations of a low-pass LTI system