Nanostructures, Technology, Research, and Applications

Contains reports on twenty research projects and a list of publications.Joint Services Electronics Program Grant DAAH04-95-1-0038National Science Foundation Grant ECS-94-07078Semiconductor Research CorporationU.S. Army Research Office Grant DAAH04-95-1-0564Defense Advanced Research Projects Agency/Naval Air Systems Command Contract N00019-95-K-0131National Aeronautics and Space Administration Contract NAS8-38249National Aeronautics and Space Administration Grant NAGW-2003IBM Corporation Contract 1622National Science Foundation Graduate FellowshipU.S. Navy - Office of Naval Research Grant N00014-95-1-1297U.S. Army Research Office Contract DAAH04-94-G-0377U.S. Air Force - Office of Scientific Research Grant F49620-92-J-0064U.S. Air Force - Office of Scientific Research Grant F49620-95-1-0311National Science Foundation Contract DMR 94-0034U.S. Air Force - Office of Scientific Research Contract F49620-96-0126Harvard-Smithsonian Astrophysical Observatory Contract SV630304National Aeronautics and Space Administration Grant NAG5-5105Los Alamos National Laboratory Contract E57800017-9

Materials and processes for advanced lithography applications

textStep and Flash Imprint Lithography (S-FIL) is a high resolution, next-generation lithography technique that uses an ambient temperature and low pressure process to replicate high resolution images in a UV-curable liquid material. Application of the S-FIL process in conjunction with multi-level imprint templates and new imprint materials enables one S-FIL step to reproduce the same structures that require two photolithography steps, thereby greatly reducing the number of patterning steps required for the copper, dual damascene process used to fabricate interconnect wirings in modern integrated circuits. Two approaches were explored for the implementation of S-FIL in the dual damascene process: sacrificial imprint materials and imprintable dielectric materials. Sacrificial imprint materials function as a pattern recording medium during S-FIL and a three-dimensional etch mask during the dielectric substrate etch, enabling the simultaneous patterning of both the via and metal structures in the dielectric substrate. Development of sacrificial imprint materials and the associated imprint and etch processes are described. Application of S-FIL and the sacrificial imprint material in a commercial copper dual damascene process successfully produced functional copper interconnect structures, demonstrating the feasibility of integrating multi-level S-FIL in the copper dual damascene process. Imprintable dielectric materials are designed to combine the multi-level patterning capability of S-FIL with novel dielectric precursor materials, enabling the simultaneous deposition and patterning of the interlayer dielectric material. Several candidate imprintable dielectric materials were evaluated: sol-gel, polyhedral oligomeric silsesquioxane (POSS) epoxide, POSS acrylate, POSS azide, and POSS thiol. POSS thiol shows the most promise as functional imprintable dielectric material, although additional work in the POSS thiol formulation and viscous dispense process are needed to produce functional interconnect structures. Integration of S-FIL with imprintable dielectric materials would enable further streamlining of the dual damascene fabrication process. The fabrication of electronic devices on flexible substrates represents an opportunity for the development of macroelectronics such as flexible displays and large area devices. Traditional optical lithography encounters alignment and overlay limitations when applied on flexible substrates. A thermally activated, dual-tone photoresist system and its associated etch process were developed to enable the simultaneous patterning of two device layers on a flexible substrate.Chemical Engineerin

Advanced information processing system for advanced launch system: Hardware technology survey and projections

The major goals of this effort are as follows: (1) to examine technology insertion options to optimize Advanced Information Processing System (AIPS) performance in the Advanced Launch System (ALS) environment; (2) to examine the AIPS concepts to ensure that valuable new technologies are not excluded from the AIPS/ALS implementations; (3) to examine advanced microprocessors applicable to AIPS/ALS, (4) to examine radiation hardening technologies applicable to AIPS/ALS; (5) to reach conclusions on AIPS hardware building blocks implementation technologies; and (6) reach conclusions on appropriate architectural improvements. The hardware building blocks are the Fault-Tolerant Processor, the Input/Output Sequencers (IOS), and the Intercomputer Interface Sequencers (ICIS)

Proceedings of the Cold Electronics Workshop

The benefits and problems of the use of cold semiconductor electronics and the research and development effort required to bring cold electronics into more widespread use were examined

JETC (Japanese Technology Evaluation Center) Panel Report on High Temperature Superconductivity in Japan

The Japanese regard success in R and D in high temperature superconductivity as an important national objective. The results of a detailed evaluation of the current state of Japanese high temperature superconductivity development are provided. The analysis was performed by a panel of technical experts drawn from U.S. industry and academia, and is based on reviews of the relevant literature and visits to Japanese government, academic and industrial laboratories. Detailed appraisals are presented on the following: Basic research; superconducting materials; large scale applications; processing of superconducting materials; superconducting electronics and thin films. In all cases, comparisons are made with the corresponding state-of-the-art in the United States